diff --git a/litex_boards/targets/1bitsquared_icebreaker.py b/litex_boards/targets/1bitsquared_icebreaker.py
index 835b865..2b61b41 100755
--- a/litex_boards/targets/1bitsquared_icebreaker.py
+++ b/litex_boards/targets/1bitsquared_icebreaker.py
@@ -90,9 +90,15 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
-        # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
+        # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
         self.submodules.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))
+        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
+        if not self.integrated_main_ram_size:
+            self.bus.add_region("main_ram", SoCRegion(
+                origin = self.bus.regions["sram"].origin + 64*kB,
+                size   = 64*kB,
+                linker = True)
+            )
 
         # SPI Flash --------------------------------------------------------------------------------
         from litespi.modules import W25Q128JV
diff --git a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
index 5147529..fd2a6ce 100755
--- a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
+++ b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
@@ -85,9 +85,15 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
-        # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
+        # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
         self.submodules.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))
+        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
+        if not self.integrated_main_ram_size:
+            self.bus.add_region("main_ram", SoCRegion(
+                origin = self.bus.regions["sram"].origin + 64*kB,
+                size   = 64*kB,
+                linker = True)
+            )
 
         # SPI Flash --------------------------------------------------------------------------------
         from litespi.modules import W25Q128JV
diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py
index 660542e..e6c47ad 100755
--- a/litex_boards/targets/kosagi_fomu.py
+++ b/litex_boards/targets/kosagi_fomu.py
@@ -95,9 +95,15 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
-        # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
+        # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
         self.submodules.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))
+        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
+        if not self.integrated_main_ram_size:
+            self.bus.add_region("main_ram", SoCRegion(
+                origin = self.bus.regions["sram"].origin + 64*kB,
+                size   = 64*kB,
+                linker = True)
+            )
 
         # SPI Flash --------------------------------------------------------------------------------
         from litespi.modules import AT25SF161, GD25Q16C, MX25R1635F, W25Q128JV