From 5bd8c4d74f11ca3c38dd698f46d993d2871b17b4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 1 Nov 2019 10:52:36 +0100 Subject: [PATCH] targets/trellisboard: use ECLKBRIDGECS to allow ECLK to reach all DDR banks (fixes Diamond build) --- litex_boards/partner/targets/trellisboard.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/litex_boards/partner/targets/trellisboard.py b/litex_boards/partner/targets/trellisboard.py index a0ef55e..e7d202d 100755 --- a/litex_boards/partner/targets/trellisboard.py +++ b/litex_boards/partner/targets/trellisboard.py @@ -55,13 +55,19 @@ class _CRG(Module): self.sync.por += If(~por_done, por_count.eq(por_count - 1)) # pll + sys2x_clk_ecsout = Signal() self.submodules.pll = pll = ECP5PLL() pll.register_clkin(clk12, 12e6) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_init, 25e6) self.specials += [ + Instance("ECLKBRIDGECS", + i_CLK0=self.cd_sys2x_i.clk, + i_SEL=0, + o_ECSOUT=sys2x_clk_ecsout, + ), Instance("ECLKSYNCB", - i_ECLKI=self.cd_sys2x_i.clk, + i_ECLKI=sys2x_clk_ecsout, i_STOP=self.stop, o_ECLKO=self.cd_sys2x.clk), Instance("CLKDIVF",