From 5cc49bafbdef6b1ae739475cbac8cb52d1139df2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 4 Jan 2021 09:41:47 +0100 Subject: [PATCH] orangecrab: Run reset_timer with por/48MHz clock domain (sys clock domain is now directly reseted on usr_btn press). --- litex_boards/targets/orangecrab.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index d959e7e..6a7c272 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -66,7 +66,8 @@ class _CRG(Module): usb_pll.create_clkout(self.cd_usb_12, 12e6) # FPGA Reset (press usr_btn for 1 second to fallback to bootloader) - reset_timer = WaitTimer(sys_clk_freq) + reset_timer = WaitTimer(int(48e6)) + reset_timer = ClockDomainsRenamer("por")(reset_timer) self.submodules += reset_timer self.comb += reset_timer.wait.eq(~rst_n) self.comb += platform.request("rst_n").eq(~reset_timer.done) @@ -83,7 +84,6 @@ class _CRGSDRAM(Module): # # # - self.stop = Signal() self.reset = Signal() @@ -136,7 +136,8 @@ class _CRGSDRAM(Module): usb_pll.create_clkout(self.cd_usb_12, 12e6) # FPGA Reset (press usr_btn for 1 second to fallback to bootloader) - reset_timer = WaitTimer(sys_clk_freq) + reset_timer = WaitTimer(int(48e6)) + reset_timer = ClockDomainsRenamer("por")(reset_timer) self.submodules += reset_timer self.comb += reset_timer.wait.eq(~rst_n) self.comb += platform.request("rst_n").eq(~reset_timer.done)