From 5d4ebeb09c7fb075b615ec56efe42320eff3b442 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 22 Jul 2024 11:40:19 +0200
Subject: [PATCH] targets: Add initial Enclustra Mercury+ XU8/PE3 target with
 DRAM and PCIe.

---
 .../targets/enclustra_mercury_xu8_pe3.py      | 133 ++++++++++++++++++
 1 file changed, 133 insertions(+)
 create mode 100755 litex_boards/targets/enclustra_mercury_xu8_pe3.py

diff --git a/litex_boards/targets/enclustra_mercury_xu8_pe3.py b/litex_boards/targets/enclustra_mercury_xu8_pe3.py
new file mode 100755
index 0000000..f6cb660
--- /dev/null
+++ b/litex_boards/targets/enclustra_mercury_xu8_pe3.py
@@ -0,0 +1,133 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2023-2024 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex.gen import *
+
+from litex_boards.platforms import enclustra_mercury_xu8_pe3
+
+from litex.soc.cores.clock import *
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
+
+from litedram.modules import MT40A256M16
+from litedram.phy import usddrphy
+
+from litepcie.phy.usppciephy import USPPCIEPHY
+from litepcie.software import generate_litepcie_software
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(LiteXModule):
+    def __init__(self, platform, sys_clk_freq):
+        self.rst       = Signal()
+        self.cd_sys    = ClockDomain()
+        self.cd_sys4x  = ClockDomain()
+        self.cd_pll4x  = ClockDomain()
+        self.cd_idelay = ClockDomain()
+
+        # # #
+
+        self.pll = pll = USMMCM(speedgrade=-1)
+        self.comb += pll.reset.eq(self.rst)
+        pll.register_clkin(platform.request("clk100"), 100e6)
+        pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
+        pll.create_clkout(self.cd_idelay, 500e6)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
+
+        self.specials += [
+            Instance("BUFGCE_DIV",
+                p_BUFGCE_DIVIDE = 4,
+                i_CE = 1,
+                i_I  = self.cd_pll4x.clk,
+                o_O  = self.cd_sys.clk,
+            ),
+            Instance("BUFGCE",
+                i_CE = 1,
+                i_I  = self.cd_pll4x.clk,
+                o_O  = self.cd_sys4x.clk,
+            ),
+        ]
+
+        self.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, sys_clk_freq=2006, with_pcie=False, with_led_chaser=True, **kwargs):
+        platform = enclustra_mercury_xu8_pe3.Platform()
+
+        # CRG --------------------------------------------------------------------------------------
+        self.crg = _CRG(platform, sys_clk_freq)
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Enclustra Mercury+ XU8/PE3", **kwargs)
+
+        # JTAGBone ---------------------------------------------------------------------------------
+        self.add_jtagbone()
+
+        # PCIe -------------------------------------------------------------------------------------
+        if with_pcie:
+            self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
+                speed      = "gen3",
+                data_width = 128,
+                bar0_size  = 0x20000,
+            )
+            self.add_pcie(phy=self.pcie_phy, ndmas=1)
+
+        # DDR4 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
+                memtype          = "DDR4",
+                sys_clk_freq     = sys_clk_freq,
+                iodelay_clk_freq = 500e6,
+            )
+            self.add_sdram("sdram",
+                phy           = self.ddrphy,
+                module        = MT40A256M16(sys_clk_freq, "1:4"),
+                l2_cache_size = kwargs.get("l2_size", 8192),
+            )
+
+        # Leds -------------------------------------------------------------------------------------
+        if with_led_chaser:
+            self.leds = LedChaser(
+                pads         = platform.request_all("user_led"),
+                sys_clk_freq = sys_clk_freq,
+            )
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    from litex.build.parser import LiteXArgumentParser
+    parser = LiteXArgumentParser(platform=enclustra_mercury_xu8_pe3.Platform, description="LiteX SoC on Enclustra Mercury+ XU8/PE3.")
+    parser.add_target_argument("--sys-clk-freq", default=125e6, type=float, help="System clock frequency.")
+    parser.add_target_argument("--with-pcie",    action="store_true",       help="Enable PCIe support.")
+    parser.add_target_argument("--driver",       action="store_true",       help="Generate PCIe driver.")
+    args = parser.parse_args()
+
+    soc = BaseSoC(
+         sys_clk_freq = args.sys_clk_freq,
+         with_pcie    = args.with_pcie,
+         **parser.soc_argdict
+    )
+    builder = Builder(soc, **parser.builder_argdict)
+    if args.build:
+        builder.build(**parser.toolchain_argdict)
+
+    if args.driver:
+        generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
+
+if __name__ == "__main__":
+    main()