diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py
index fa46d46..6860a7d 100755
--- a/litex_boards/targets/colorlight_5a_75x.py
+++ b/litex_boards/targets/colorlight_5a_75x.py
@@ -138,7 +138,7 @@ class BaseSoC(SoCCore):
             **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
-        with_rst = kwargs["uart_name"] not in ["serial", "bridge"] # serial_rx shared with user_btn_n.
+        with_rst = kwargs["uart_name"] not in ["serial", "crossover"] # serial_rx shared with user_btn_n.
         with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
         self.submodules.crg = _CRG(platform, sys_clk_freq, use_internal_osc=use_internal_osc, with_usb_pll=with_usb_pll,with_rst=with_rst, sdram_rate=sdram_rate)
 
diff --git a/litex_boards/targets/decklink_quad_hdmi_recorder.py b/litex_boards/targets/decklink_quad_hdmi_recorder.py
index 1561785..757af96 100755
--- a/litex_boards/targets/decklink_quad_hdmi_recorder.py
+++ b/litex_boards/targets/decklink_quad_hdmi_recorder.py
@@ -11,7 +11,7 @@
 #
 # Use:
 # litex_server --jtag --jtag-config=openocd_xc7_ft232.cfg
-# litex_term bridge
+# litex_term crossover
 
 import os
 import argparse
diff --git a/litex_boards/targets/gsd_butterstick.py b/litex_boards/targets/gsd_butterstick.py
index 0f59718..29b4b0a 100755
--- a/litex_boards/targets/gsd_butterstick.py
+++ b/litex_boards/targets/gsd_butterstick.py
@@ -10,7 +10,7 @@
 # Build/Use:
 # ./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
 # litex_server --udp
-# litex_term bridge
+# litex_term crossover
 
 import os
 import sys
diff --git a/litex_boards/targets/lattice_ice40up5k_evn.py b/litex_boards/targets/lattice_ice40up5k_evn.py
index ab9d6bb..c19f5b6 100755
--- a/litex_boards/targets/lattice_ice40up5k_evn.py
+++ b/litex_boards/targets/lattice_ice40up5k_evn.py
@@ -100,16 +100,10 @@ class BaseSoC(SoCCore):
                 pads         = platform.request_all("user_led_n"),
                 sys_clk_freq = sys_clk_freq)
 
-        # Add a UART-Wishbone bridge -----------------------------------------
-        debug_uart=False
+        # Add a UARTBone bridge --------------------------------------------------------------------
+        debug_uart = False
         if debug_uart:
-            # This will add a bridge on the second serial port defined in platform
-            from litex.soc.cores.uart import UARTWishboneBridge
-            self.submodules.uart_bridge = UARTWishboneBridge(
-                platform.request("serial"),
-                sys_clk_freq,
-                baudrate=115200)
-            self.add_wb_master(self.uart_bridge.wishbone)
+            self.add_uartbone(name="serial")
 
 # Flash --------------------------------------------------------------------------------------------