From 5f694166ce6aa52b57d7c0ec17553ea0b90ce778 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 19 Oct 2023 06:26:10 +0200 Subject: [PATCH] platforms/sipeed_tang_primer_25k: swap UART TX & RX, fix TX pin (J1:20 -> J1:21) --- litex_boards/platforms/sipeed_tang_primer_25k.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/platforms/sipeed_tang_primer_25k.py b/litex_boards/platforms/sipeed_tang_primer_25k.py index cd90bae..0263a97 100644 --- a/litex_boards/platforms/sipeed_tang_primer_25k.py +++ b/litex_boards/platforms/sipeed_tang_primer_25k.py @@ -75,8 +75,8 @@ _connectors = [ _dock_io = [ # Serial. ("serial", 0, - Subsignal("rx", Pins("J1:20")), - Subsignal("tx", Pins("J1:19")), + Subsignal("rx", Pins("J1:19")), + Subsignal("tx", Pins("J1:21")), IOStandard("LVCMOS33") ),