diff --git a/litex_boards/official/targets/arty.py b/litex_boards/official/targets/arty.py index 95346b0..6ccd8f0 100755 --- a/litex_boards/official/targets/arty.py +++ b/litex_boards/official/targets/arty.py @@ -8,6 +8,7 @@ import argparse from migen import * from litex_boards.platforms import arty +from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * @@ -51,10 +52,10 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(100e6), **kwargs): + def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): platform = arty.Platform() SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, + integrated_rom_size=integrated_rom_size, integrated_sram_size=0x8000, **kwargs) @@ -77,7 +78,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, **kwargs) + BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"), self.platform.request("eth")) @@ -105,6 +106,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Arty") builder_args(parser) soc_sdram_args(parser) + vivado_build_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") args = parser.parse_args() @@ -112,7 +114,7 @@ def main(): cls = EthernetSoC if args.with_ethernet else BaseSoC soc = cls(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(**vivado_build_argdict(args)) if __name__ == "__main__": diff --git a/litex_boards/official/targets/nexys4ddr.py b/litex_boards/official/targets/nexys4ddr.py index 14f35ad..bcc0f27 100755 --- a/litex_boards/official/targets/nexys4ddr.py +++ b/litex_boards/official/targets/nexys4ddr.py @@ -49,10 +49,10 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(100e6), **kwargs): + def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): platform = nexys4ddr.Platform() SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, + integrated_rom_size=integrated_rom_size, integrated_sram_size=0x8000, **kwargs) @@ -76,7 +76,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, **kwargs) + BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) diff --git a/litex_boards/partner/targets/trellisboard.py b/litex_boards/partner/targets/trellisboard.py index 8654bf3..627b9ff 100755 --- a/litex_boards/partner/targets/trellisboard.py +++ b/litex_boards/partner/targets/trellisboard.py @@ -78,10 +78,10 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs): + def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs): platform = trellisboard.Platform(toolchain=toolchain) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, + integrated_rom_size=integrated_rom_size, **kwargs) # crg @@ -109,7 +109,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, toolchain="diamond", **kwargs): - BaseSoC.__init__(self, toolchain=toolchain, **kwargs) + BaseSoC.__init__(self, toolchain=toolchain, integrated_rom_size=0x10000, **kwargs) self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"),