From 5f8ac853b153de6204e78d335fc68cf0707eb1fc Mon Sep 17 00:00:00 2001
From: Liana Koleva <43767763+lianakoleva@users.noreply.github.com>
Date: Mon, 25 Sep 2023 12:50:30 +0200
Subject: [PATCH] Resolve High Density bank IOStandard error

This resolves the following error during `build` on Vivado 2023.1:
```ERROR: [DRC BIVB-1] Bank IO standard Support: Bank 47 has incompatible IO(s) because: The LVDS I/O standard is not supported for banks of type High Density. Move the following ports or change their properties:
clk125_p```
---
 litex_boards/platforms/xilinx_zcu102.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/litex_boards/platforms/xilinx_zcu102.py b/litex_boards/platforms/xilinx_zcu102.py
index 17b2fe3..8e7aa70 100644
--- a/litex_boards/platforms/xilinx_zcu102.py
+++ b/litex_boards/platforms/xilinx_zcu102.py
@@ -13,8 +13,8 @@ from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer
 _io = [
     # Clk / Rst
     ("clk125", 0,
-        Subsignal("p", Pins("G21"), IOStandard("LVDS")),
-        Subsignal("n", Pins("F21"), IOStandard("LVDS")),
+        Subsignal("p", Pins("G21"), IOStandard("LVDS_25")),
+        Subsignal("n", Pins("F21"), IOStandard("LVDS_25")),
     ),
     ("clk300", 0,
         Subsignal("p", Pins("AL8"), IOStandard("DIFF_SSTL12_DCI")),