From 542001dddf549927754a8b513cc451687b01da5d Mon Sep 17 00:00:00 2001 From: gatecat Date: Fri, 5 Mar 2021 11:18:37 +0000 Subject: [PATCH 1/2] crosslink_nx_vip: Split camera MCLK to its own resource Signed-off-by: gatecat --- litex_boards/platforms/crosslink_nx_vip.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/litex_boards/platforms/crosslink_nx_vip.py b/litex_boards/platforms/crosslink_nx_vip.py index 0ad4798..ddcd5e5 100644 --- a/litex_boards/platforms/crosslink_nx_vip.py +++ b/litex_boards/platforms/crosslink_nx_vip.py @@ -112,31 +112,32 @@ _io = [ Misc("SLEWRATE=FAST") ), + ("camera_mclk", 0, Pins("M3"), IOStandard("LVCMOS18")), + ("camera_mclk", 1, Pins("M4"), IOStandard("LVCMOS18")), + ("camera_mclk", 2, Pins("M5"), IOStandard("LVCMOS18")), + ("camera_mclk", 3, Pins("M6"), IOStandard("LVCMOS18")), + # MIPI camera modules # Note that use of MIPI_DPHY standard for + and LVCMOS12H for - is copied from Lattice PDC ("camera", 0, - Subsignal("mclk", Pins("M3"), IOStandard("LVCMOS18")), Subsignal("clkp", Pins("A2"), IOStandard("MIPI_DPHY")), Subsignal("clkn", Pins("B1"), IOStandard("LVCMOS12H")), Subsignal("dp", Pins("B2 A3 C2 A4"), IOStandard("MIPI_DPHY")), Subsignal("dn", Pins("C1 B3 D1 B4"), IOStandard("LVCMOS12H")), ), ("camera", 1, - Subsignal("mclk", Pins("M4"), IOStandard("LVCMOS18")), Subsignal("clkp", Pins("A8"), IOStandard("MIPI_DPHY")), Subsignal("clkn", Pins("B8"), IOStandard("LVCMOS12H")), Subsignal("dp", Pins("A7 A9 A6 A10"), IOStandard("MIPI_DPHY")), Subsignal("dn", Pins("B7 B9 B6 B10"), IOStandard("LVCMOS12H")), ), ("camera", 2, - Subsignal("mclk", Pins("M5"), IOStandard("LVCMOS18")), Subsignal("clkp", Pins("W11"), IOStandard("MIPI_DPHY")), Subsignal("clkn", Pins("Y11"), IOStandard("LVCMOS12H")), Subsignal("dp", Pins("V11 W13 U12 R12"), IOStandard("MIPI_DPHY")), Subsignal("dn", Pins("U11 V12 T12 P12"), IOStandard("LVCMOS12H")), ), ("camera", 3, - Subsignal("mclk", Pins("M6"), IOStandard("LVCMOS18")), Subsignal("clkp", Pins("T13"), IOStandard("MIPI_DPHY")), Subsignal("clkn", Pins("T14"), IOStandard("LVCMOS12H")), Subsignal("dp", Pins("Y15 U15 V17 P13"), IOStandard("MIPI_DPHY")), From 547157c9ca0b4c45d018d2bb91a957eb8e7a1040 Mon Sep 17 00:00:00 2001 From: gatecat Date: Fri, 5 Mar 2021 11:26:56 +0000 Subject: [PATCH 2/2] crosslink_nx_vip: Fix cam_reset IO configuration Signed-off-by: gatecat --- litex_boards/platforms/crosslink_nx_vip.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/platforms/crosslink_nx_vip.py b/litex_boards/platforms/crosslink_nx_vip.py index ddcd5e5..d125310 100644 --- a/litex_boards/platforms/crosslink_nx_vip.py +++ b/litex_boards/platforms/crosslink_nx_vip.py @@ -22,7 +22,7 @@ _io = [ ("clk27_3", 0, Pins("Y2"), IOStandard("LVCMOS18")), # 8.1. General Purpose Push Buttons - all logic zero when pressed] - ("cam_reset", 0, Pins("T1"), IOStandard("LVCMOS18")), # SW1 + ("cam_reset", 0, Pins("T1"), IOStandard("LVCMOS18H"), Misc("PULLMODE=UP")), # SW1 ("gsrn", 0, Pins("G13"), IOStandard("LVCMOS33")), # SW3 ("programn", 0, Pins("E11"), IOStandard("LVCMOS33")), # SW4 ("user_btn", 0, Pins("L20"), IOStandard("LVCMOS33")), # SW5