From 618f41bb1e318c005a9b315d963e2d5e66d03de9 Mon Sep 17 00:00:00 2001 From: Arnaud Durand Date: Thu, 22 Aug 2019 02:27:50 +0200 Subject: [PATCH] Update ecp5_evn.py The system clock was driven directly while it should be driven by the PLL. --- litex_boards/community/targets/ecp5_evn.py | 1 - 1 file changed, 1 deletion(-) diff --git a/litex_boards/community/targets/ecp5_evn.py b/litex_boards/community/targets/ecp5_evn.py index 3b1a766..a276855 100755 --- a/litex_boards/community/targets/ecp5_evn.py +++ b/litex_boards/community/targets/ecp5_evn.py @@ -39,7 +39,6 @@ class _CRG(Module): pll.register_clkin(clk, x5_clk_freq or 12e6) pll.create_clkout(self.cd_sys, sys_clk_freq) self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n) - self.comb += self.cd_sys.clk.eq(clk) # BaseSoC ------------------------------------------------------------------------------------------