From d1096a2cd026f912cd3c0faa8bdc8334861e9e70 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Wed, 11 May 2022 08:58:50 +0700 Subject: [PATCH 1/4] Add HPC Store XC7K420T board --- litex_boards/platforms/hpcstore_xc7k420t.py | 338 ++++++++++++++++++++ litex_boards/targets/hpcstore_xc7k420t.py | 163 ++++++++++ 2 files changed, 501 insertions(+) create mode 100644 litex_boards/platforms/hpcstore_xc7k420t.py create mode 100755 litex_boards/targets/hpcstore_xc7k420t.py diff --git a/litex_boards/platforms/hpcstore_xc7k420t.py b/litex_boards/platforms/hpcstore_xc7k420t.py new file mode 100644 index 0000000..f90e101 --- /dev/null +++ b/litex_boards/platforms/hpcstore_xc7k420t.py @@ -0,0 +1,338 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2020 Hans Baier +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform +from litex.build.openocd import OpenOCD + +# Board support for this chinese Kintex 420T board by "HPC FPGA Board Store" +# https://www.aliexpress.com/item/1005001631827738.html + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Clk / Rst + ("clk100", 0, Pins("U24"), IOStandard("LVCMOS33")), + ("diffclk100", 0, + Subsignal("p", Pins("U22"), IOStandard("LVDS_25")), + Subsignal("n", Pins("U23"), IOStandard("LVDS_25")) + ), + + # Leds + ("user_led_n", 0, Pins("A27"), IOStandard("LVCMOS15")), + ("user_led_n", 1, Pins("E24"), IOStandard("LVCMOS15")), + ("user_led_n", 2, Pins("G24"), IOStandard("LVCMOS15")), + ("user_led_n", 3, Pins("H21"), IOStandard("LVCMOS15")), + ("user_led_n", 4, Pins("G27"), IOStandard("LVCMOS15")), + ("user_led_n", 5, Pins("H26"), IOStandard("LVCMOS15")), + ("user_led_n", 6, Pins("H25"), IOStandard("LVCMOS15")), + ("user_led_n", 7, Pins("H24"), IOStandard("LVCMOS15")), + + # Buttons + ("user_btn_n", 0, Pins("Y23"), IOStandard("LVCMOS15")), + ("user_btn_n", 1, Pins("J24"), IOStandard("LVCMOS15")), # J4 jumper 2.5V or 3.3V + + # I2C / AT24C04 + ("i2c", 0, + Subsignal("scl", Pins("C17")), + Subsignal("sda", Pins("C16")), + IOStandard("LVCMOS33") + ), + + # Serial + ("serial", 0, + Subsignal("tx", Pins("D16")), # CH340_TX + Subsignal("rx", Pins("D17")), # CH340_RX + IOStandard("LVCMOS33") + ), + + # DDR3 SDRAM near SFP ports + ("ddram", 0, + Subsignal("a", Pins( + "F28 E29 F26 D29 B29 C30 A30 B28 C29 B30 E30 E26 A28 H29 F25"), + IOStandard("SSTL15")), + Subsignal("ba", Pins("F30 G28 E28"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("H27"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("G30"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("G29"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("H30"), IOStandard("SSTL15")), + Subsignal("dm", Pins( + "B22 E19 F22 K19 M23 P18 P26 N29"), + IOStandard("SSTL15")), + Subsignal("dq", Pins( + "A21 A22 A23 B23 B19 C19 A20 B20 C21 D21 C22 D22 E18 D18 E20 E21" + \ + "G18 F18 G20 F20 H20 G22 G23 F23 L18 J18 J19 K20 J22 H22 K23 J23" + \ + "N24 N22 P24 P23 L20 M22 M24 N25 M17 N19 N17 P17 N20 N21 P21 P19" + \ + "K26 K25 L26 L25 M25 N26 P28 P27 L30 M29 P29 R29 K28 K29 K30 M28"), + IOStandard("SSTL15_T_DCI")), + Subsignal("dqs_p", Pins("B18 E23 H19 K21 L23 M18 N27 N30"), + IOStandard("DIFF_SSTL15")), + Subsignal("dqs_n", Pins("A18 D23 G19 J21 K24 M19 M27 M30"), + IOStandard("DIFF_SSTL15")), + Subsignal("clk_p", Pins("J26"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_n", Pins("J27"), IOStandard("DIFF_SSTL15")), + Subsignal("cke", Pins("G25"), IOStandard("SSTL15")), + Subsignal("odt", Pins("J28"), IOStandard("SSTL15")), + Subsignal("reset_n", Pins("F27"), IOStandard("LVCMOS15")), + Misc("SLEW=FAST"), + Misc("VCCAUX_IO=NORMAL") + ), + + # DDR3 SDRAM near power supply + ("ddram", 1, + Subsignal("a", Pins( + "AG22 AJ23 AF22 AJ26 AG23 AD23 AF23 AJ24 AE23 AB23 AJ22 AK25 AD21 AD22 AK24"), + IOStandard("SSTL15")), + Subsignal("ba", Pins("AK23 AF21 AC21"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("AF20"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("AK21"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("AJ21"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("AE21"), IOStandard("SSTL15")), + Subsignal("dm", Pins( + "AA28 AA27 AE28 AH30 AB18 AJ19 AD14 AK16"), + IOStandard("SSTL15")), + Subsignal("dq", Pins( + "W29 Y29 AB30 AB29 W28 W26 Y28 AB28 AA25 AD27 AB24 AC24 Y26 Y25 AA26 AC26" + \ + "AD29 AE30 AE29 AF30 AD28 AC27 AF28 AF27 AG30 AG29 AH29 AJ29 AK30 AK29 AK28 AG27" + \ + "AD18 AD19 AA18 Y18 AE18 Y19 AB17 AA17 AH20 AH19 AG19 AF18 AJ18 AK18 AJ17 AJ16" + \ + "AF16 AE16 AE15 AF15 AC15 AB15 AC14 AB14 AH17 AH16 AK14 AJ14 AF17 AG17 AH15 AH14"), + IOStandard("SSTL15_T_DCI")), + Subsignal("dqs_p", Pins("Y30 AB25 AC29 AJ27 AC17 AK19 AC16 AG14"), + IOStandard("DIFF_SSTL15")), + Subsignal("dqs_n", Pins("AA30 AC25 AC30 AJ28 AD17 AK20 AD16 AG15"), + IOStandard("DIFF_SSTL15")), + Subsignal("clk_p", Pins("AA22"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_n", Pins("AA23"), IOStandard("DIFF_SSTL15")), + Subsignal("cke", Pins("AB22"), IOStandard("SSTL15")), + Subsignal("odt", Pins("AH24"), IOStandard("SSTL15")), + Subsignal("reset_n", Pins("Y21"), IOStandard("LVCMOS15")), + Misc("SLEW=FAST"), + Misc("VCCAUX_IO=NORMAL") + ), + + # Sata + ("sata", 0, + Subsignal("rx_p", Pins("C12")), + Subsignal("rx_n", Pins("C11")), + Subsignal("tx_p", Pins("A12")), + Subsignal("tx_n", Pins("A11")), + IOStandard("LVDS"), + ), + ("sata", 1, + Subsignal("rx_p", Pins("E12")), + Subsignal("rx_n", Pins("E11")), + Subsignal("tx_p", Pins("B10")), + Subsignal("tx_n", Pins("B9")), + IOStandard("LVDS"), + ), + + # PCIe + ("pcie_x1", 0, + Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")), + Subsignal("clk_p", Pins("T6")), + Subsignal("clk_n", Pins("T5")), + Subsignal("rx_p", Pins("P6")), + Subsignal("rx_n", Pins("P5")), + Subsignal("tx_p", Pins("N4")), + Subsignal("tx_n", Pins("N3")) + ), + ("pcie_x2", 0, + Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")), + Subsignal("clk_p", Pins("T6")), + Subsignal("clk_n", Pins("T5")), + Subsignal("rx_p", Pins("")), + Subsignal("rx_p", Pins("P6 R4")), + Subsignal("rx_n", Pins("P5 R3")), + Subsignal("tx_p", Pins("N4 P2")), + Subsignal("tx_n", Pins("N3 P1")) + ), + ("pcie_x4", 0, + Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")), + Subsignal("clk_p", Pins("T6")), + Subsignal("clk_n", Pins("T5")), + Subsignal("rx_p", Pins("P6 R4 U4 V6")), + Subsignal("rx_n", Pins("P5 R3 U3 V5")), + Subsignal("tx_p", Pins("N4 P2 T2 V2")), + Subsignal("tx_n", Pins("N3 P1 T1 V1")) + ), + ("pcie_x8", 0, + Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS33")), + Subsignal("clk_p", Pins("T6")), + Subsignal("clk_n", Pins("T5")), + Subsignal("rx_p", Pins("P6 R4 U4 V6 W4 Y6 AA4 AB6")), + Subsignal("rx_n", Pins("P5 R3 U3 V5 W3 Y5 AA3 AB5")), + Subsignal("tx_p", Pins("N4 P2 T2 V2 Y2 AB2 AD2 AF2")), + Subsignal("tx_n", Pins("N3 P1 T1 V1 Y1 AB1 AD1 AF1")) + ), + + + # SFP + ("sfp_a", 0, # SFP A + Subsignal("txp", Pins("A8")), + Subsignal("txn", Pins("A7")), + Subsignal("rxp", Pins("D10")), + Subsignal("rxn", Pins("D9")), + Subsignal("sda", Pins("C15")), + Subsignal("scl", Pins("A15")), + ), + ("sfp_a_tx", 0, # SFP A + Subsignal("p", Pins("A8")), + Subsignal("n", Pins("A7")) + ), + ("sfp_a_rx", 0, # SFP A + Subsignal("p", Pins("D10")), + Subsignal("n", Pins("D9")) + ), + ("sfp_b", 0, # SFP B + Subsignal("txp", Pins("C8")), + Subsignal("txn", Pins("C7")), + Subsignal("rxp", Pins("F10")), + Subsignal("rxn", Pins("F9")), + Subsignal("sda", Pins("C14")), + Subsignal("scl", Pins("B14")), + ), + ("sfp_b_tx", 0, # SFP B + Subsignal("p", Pins("C8")), + Subsignal("n", Pins("C7")) + ), + ("sfp_b_rx", 0, # SFP B + Subsignal("p", Pins("F10")), + Subsignal("n", Pins("F9")) + ), +] + +# Connectors --------------------------------------------------------------------------------------- + +# +# Connector layout on the board +# ┌────────────────────────────────────────┐ +# │ 2 80 │ +# │ ┌──────────────────────────────┐ │ +# └──┐ └──────────────────────────────┘ ┌──┘ +# │ 1 79 │ +# └──────────────────────────────────┘ +# +_connectors = [ + # Connector on the SFP side + ("BTB_A", { + # 1: "GND", 2: "GND", + 3: "A16", 4: "B24", + 5: "B17", 6: "D24", + # 7: "GND", 8: "GND", + 9: "E16", 10: "A14", + 11: "F16", 12: "B15", + 13: "R25", 14: "U30", + 15: "R24", 16: "U29", + # 17: "GND", 18: "GND", + 19: "R21", 20: "T27", + 21: "R20", 22: "R26", + 23: "T23", 24: "U28", + 25: "R23", 26: "U27", + # 27: "GND", 28: "GND", + 29: "T18", 30: "V25", + 31: "T17", 32: "V24", + 33: "V20", 34: "R19", + 35: "U20", 36: "R18", + # 37: "GND", 38: "GND", + 39: "W23", 40: "T21", + 41: "W22", 42: "T20", + 43: "U18", 44: "V19", + 45: "U17", 46: "U19", + # 47: "GND", 48: "GND", + 49: "T26", 50: "W17", + 51: "T25", 52: "V17", + 53: "V22", 54: "W19", + 55: "V21", 56: "W18", + # 57: "GND", 58: "GND", + 59: "C24", 60: "T22", + 61: "D26", 62: "V30", + 63: "C27", 64: "U25", + 65: "B27", 66: "AF25", + # 67: "GND", 68: "GND"x + 69: "Y24", 70: "AH26", + 71: "AE26", 72: "AG25", + 73: "AD26", 74: "AH25", + # 75: "GND", 76: "GND" + # 77: "NC", 78: "3V3" + # 79: "NC", 80: "3V3" + }), + + # Connector on the power side + ("BTB_B", { + # 1: "GND", 2: "GND", + 3: "AJ11", 4: "AK9", + 5: "AJ12", 6: "AK10", + # 7: "GND", 8: "GND", + 9: "AJ7", 10: "AG11", + 11: "AJ8", 12: "AG12", + # 13: "GND", 14: "GND", + 15: "AF9", 16: "AG7", + 17: "AF10", 18: "AG8", + # 19: "GND", 20: "GND", + 21: "AE11", 22: "AH9", + 23: "AE12", 24: "AH10", + # 25: "GND", 26: "GND", + 27: "AE8", 28: "AF6", + 29: "AE7", 30: "AF5", + # 31: "GND", 32: "GND", + 33: "AG3", 34: "AK5", + 35: "AG4", 36: "AK6", + # 37: "GND", 38: "GND", + 39: "AE3", 40: "AH5", + 41: "AE4", 42: "AH6", + # 43: "GND", 44: "GND", + 45: "AK1", 46: "AJ3", + 47: "AK2", 48: "AJ4", + # 49: "GND", 50: "GND", + 51: "AC3", 52: "AH1", + 53: "AC4", 54: "AH2", + # 55: "GND", 56: "GND", + 58: "AC19", + 59: "L17", 60: "AB19", + # 61: "GND", 62: "GND", + 63: "AC20", 64: "AB20", + 65: "AE20", 66: "AA20", + # 67: "GND", 68: "GND", + 69: "W24", 70: "Y20", + 72: "AA21", + # 73: "GND", 74: "GND", + # 75: "NC", 76: "GND", + # 77: "VCC12V", 78: "VCC3.3V", + # 79: "VCC12V", 80: "VCC3.3V", + }), +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(XilinxPlatform): + default_clk_name = "diffclk100" + default_clk_period = 1e9/100e6 + + def __init__(self): + XilinxPlatform.__init__(self, "xc7k420t-ffg901-2", _io, _connectors, toolchain="ISE") + self.add_platform_command(""" + set_property CONFIG_VOLTAGE 3.3 [current_design] + set_property CFGBVS VCCO [current_design] + """) + self.toolchain.bitstream_commands = [ + "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", + "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", + "set_property BITSTREAM.CONFIG.CCLK_TRISTATE TRUE [current_design]", + "set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]", + "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]", + "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", + "set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]", + "set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]", + ] + self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 32 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] + + def create_programmer(self): + return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a420t.bit") + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) + self.add_period_constraint(self.lookup_request("diffclk100", loose=True), 1e9/100e6) diff --git a/litex_boards/targets/hpcstore_xc7k420t.py b/litex_boards/targets/hpcstore_xc7k420t.py new file mode 100755 index 0000000..d99be11 --- /dev/null +++ b/litex_boards/targets/hpcstore_xc7k420t.py @@ -0,0 +1,163 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2022 Andrew Gillham +# Copyright (c) 2014-2015 Sebastien Bourdeauducq +# Copyright (c) 2014-2020 Florent Kermarrec +# Copyright (c) 2014-2015 Yann Sionneau +# Copyright (c) 2020 Hans Baier +# SPDX-License-Identifier: BSD-2-Clause + +# Board support for this chinese Kintex 420T board by "HPC FPGA Board Store" +# https://www.aliexpress.com/item/1005001631827738.html + +import os + +from migen import * + +from litex_boards.platforms import aliexpress_stlv7325 + +from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser +from litex.soc.cores.bitbang import I2CMaster + +from litedram.modules import MT8JTF12864 +from litedram.phy import s7ddrphy + +from litepcie.phy.s7pciephy import S7PCIEPHY +from litepcie.software import generate_litepcie_software + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.rst = Signal() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() + + # # # + + # Clk/Rst. + clk100 = platform.request("diffclk100") + rst_n = platform.request("cpu_reset_n") + + # PLL. + self.submodules.pll = pll = S7MMCM(speedgrade=-2) + self.comb += pll.reset.eq(~rst_n | self.rst) + pll.register_clkin(clk100, 100e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_idelay, 200e6) + platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. + + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(100e6), + with_led_chaser = True, + with_pcie = False, + with_sata = False, + **kwargs): + platform = aliexpress_stlv7325.Platform() + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on HPC Store XC7K420T", **kwargs) + + # DDR3 SDRAM ------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), + memtype = "DDR3", + nphases = 4, + sys_clk_freq = sys_clk_freq, + ) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT8JTF12864(sys_clk_freq, "1:4"), + l2_cache_size = kwargs.get("l2_size", 8192), + ) + + # PCIe ------------------------------------------------------------------------------------- + if with_pcie: + self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), + data_width = 128, + bar0_size = 0x20000) + self.add_pcie(phy=self.pcie_phy, ndmas=1) + + # TODO verify / test + # SATA ------------------------------------------------------------------------------------- + if with_sata: + from litex.build.generic_platform import Subsignal, Pins + from litesata.phy import LiteSATAPHY + + # RefClk, Generate 150MHz from PLL. + self.clock_domains.cd_sata_refclk = ClockDomain() + self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6) + sata_refclk = ClockSignal("sata_refclk") + platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]") + + # PHY + self.submodules.sata_phy = LiteSATAPHY(platform.device, + refclk = sata_refclk, + pads = platform.request("sata", 0), + gen = "gen2", + clk_freq = sys_clk_freq, + data_width = 16) + + # Core + self.add_sata(phy=self.sata_phy, mode="read+write") + + # Leds ------------------------------------------------------------------------------------- + if with_led_chaser: + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led_n"), + sys_clk_freq = sys_clk_freq) + + # I2C -------------------------------------------------------------------------------------- + self.submodules.i2c = I2CMaster(platform.request("i2c")) + +# Build -------------------------------------------------------------------------------------------- + +def main(): + from litex.soc.integration.soc import LiteXSoCArgumentParser + parser = LiteXSoCArgumentParser(description="LiteX SoC on AliExpress HPC Store XC7K420T") + target_group = parser.add_argument_group(title="Target options") + target_group.add_argument("--build", action="store_true", help="Build design.") + target_group.add_argument("--load", action="store_true", help="Load bitstream.") + target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") + ethopts = target_group.add_mutually_exclusive_group() + target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.") + target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.") + target_group.add_argument("--with-sata", action="store_true", help="Enable SATA support.") + builder_args(parser) + soc_core_args(parser) + args = parser.parse_args() + + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_pcie = args.with_pcie, + with_sata = args.with_sata, + **soc_core_argdict(args) + ) + builder = Builder(soc, **builder_argdict(args)) + if args.build: + builder.build() + + if args.driver: + generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) + +if __name__ == "__main__": + main() From f383ad3938584703737be5cb7a4e115cfb98a3bf Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Wed, 11 May 2022 10:20:49 +0700 Subject: [PATCH 2/4] Support HPC Store XC7K420T board --- litex_boards/platforms/hpcstore_xc7k420t.py | 380 ++++++++++---------- litex_boards/targets/hpcstore_xc7k420t.py | 38 +- 2 files changed, 216 insertions(+), 202 deletions(-) diff --git a/litex_boards/platforms/hpcstore_xc7k420t.py b/litex_boards/platforms/hpcstore_xc7k420t.py index f90e101..4b1970a 100644 --- a/litex_boards/platforms/hpcstore_xc7k420t.py +++ b/litex_boards/platforms/hpcstore_xc7k420t.py @@ -13,196 +13,202 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- -_io = [ - # Clk / Rst - ("clk100", 0, Pins("U24"), IOStandard("LVCMOS33")), - ("diffclk100", 0, - Subsignal("p", Pins("U22"), IOStandard("LVDS_25")), - Subsignal("n", Pins("U23"), IOStandard("LVDS_25")) - ), +def _get_io(io_standard): + _io = [ + # Clk / Rst + ("clk100", 0, Pins("U24"), io_standard), - # Leds - ("user_led_n", 0, Pins("A27"), IOStandard("LVCMOS15")), - ("user_led_n", 1, Pins("E24"), IOStandard("LVCMOS15")), - ("user_led_n", 2, Pins("G24"), IOStandard("LVCMOS15")), - ("user_led_n", 3, Pins("H21"), IOStandard("LVCMOS15")), - ("user_led_n", 4, Pins("G27"), IOStandard("LVCMOS15")), - ("user_led_n", 5, Pins("H26"), IOStandard("LVCMOS15")), - ("user_led_n", 6, Pins("H25"), IOStandard("LVCMOS15")), - ("user_led_n", 7, Pins("H24"), IOStandard("LVCMOS15")), + ("diffclk100", 0, + Subsignal("p", Pins("U22"), IOStandard("LVDS_25")), + Subsignal("n", Pins("U23"), IOStandard("LVDS_25")) + ), - # Buttons - ("user_btn_n", 0, Pins("Y23"), IOStandard("LVCMOS15")), - ("user_btn_n", 1, Pins("J24"), IOStandard("LVCMOS15")), # J4 jumper 2.5V or 3.3V + # Leds + ("user_led_n", 0, Pins("A27"), IOStandard("LVCMOS15")), + ("user_led_n", 1, Pins("E24"), IOStandard("LVCMOS15")), + ("user_led_n", 2, Pins("G24"), IOStandard("LVCMOS15")), + ("user_led_n", 3, Pins("H21"), IOStandard("LVCMOS15")), + ("user_led_n", 4, Pins("G27"), IOStandard("LVCMOS15")), + ("user_led_n", 5, Pins("H26"), IOStandard("LVCMOS15")), + ("user_led_n", 6, Pins("H25"), IOStandard("LVCMOS15")), + ("user_led_n", 7, Pins("H24"), IOStandard("LVCMOS15")), - # I2C / AT24C04 - ("i2c", 0, - Subsignal("scl", Pins("C17")), - Subsignal("sda", Pins("C16")), - IOStandard("LVCMOS33") - ), + # Buttons + ("user_btn_n", 0, Pins("Y23"), IOStandard("LVCMOS15")), + ("cpu_reset_n", 0, Pins("J24"), IOStandard("LVCMOS15")), # J4 jumper 2.5V or 3.3V - # Serial - ("serial", 0, - Subsignal("tx", Pins("D16")), # CH340_TX - Subsignal("rx", Pins("D17")), # CH340_RX - IOStandard("LVCMOS33") - ), + # I2C / AT24C04 + ("i2c", 0, + Subsignal("scl", Pins("C17")), + Subsignal("sda", Pins("C16")), + IOStandard("LVCMOS33") + ), - # DDR3 SDRAM near SFP ports - ("ddram", 0, - Subsignal("a", Pins( - "F28 E29 F26 D29 B29 C30 A30 B28 C29 B30 E30 E26 A28 H29 F25"), - IOStandard("SSTL15")), - Subsignal("ba", Pins("F30 G28 E28"), IOStandard("SSTL15")), - Subsignal("ras_n", Pins("H27"), IOStandard("SSTL15")), - Subsignal("cas_n", Pins("G30"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("G29"), IOStandard("SSTL15")), - Subsignal("cs_n", Pins("H30"), IOStandard("SSTL15")), - Subsignal("dm", Pins( - "B22 E19 F22 K19 M23 P18 P26 N29"), - IOStandard("SSTL15")), - Subsignal("dq", Pins( - "A21 A22 A23 B23 B19 C19 A20 B20 C21 D21 C22 D22 E18 D18 E20 E21" + \ - "G18 F18 G20 F20 H20 G22 G23 F23 L18 J18 J19 K20 J22 H22 K23 J23" + \ - "N24 N22 P24 P23 L20 M22 M24 N25 M17 N19 N17 P17 N20 N21 P21 P19" + \ - "K26 K25 L26 L25 M25 N26 P28 P27 L30 M29 P29 R29 K28 K29 K30 M28"), - IOStandard("SSTL15_T_DCI")), - Subsignal("dqs_p", Pins("B18 E23 H19 K21 L23 M18 N27 N30"), - IOStandard("DIFF_SSTL15")), - Subsignal("dqs_n", Pins("A18 D23 G19 J21 K24 M19 M27 M30"), - IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("J26"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("J27"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("G25"), IOStandard("SSTL15")), - Subsignal("odt", Pins("J28"), IOStandard("SSTL15")), - Subsignal("reset_n", Pins("F27"), IOStandard("LVCMOS15")), - Misc("SLEW=FAST"), - Misc("VCCAUX_IO=NORMAL") - ), + # Serial + ("serial", 0, + Subsignal("tx", Pins("D16")), # CH340_TX + Subsignal("rx", Pins("D17")), # CH340_RX + IOStandard("LVCMOS33") + ), - # DDR3 SDRAM near power supply - ("ddram", 1, - Subsignal("a", Pins( - "AG22 AJ23 AF22 AJ26 AG23 AD23 AF23 AJ24 AE23 AB23 AJ22 AK25 AD21 AD22 AK24"), - IOStandard("SSTL15")), - Subsignal("ba", Pins("AK23 AF21 AC21"), IOStandard("SSTL15")), - Subsignal("ras_n", Pins("AF20"), IOStandard("SSTL15")), - Subsignal("cas_n", Pins("AK21"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("AJ21"), IOStandard("SSTL15")), - Subsignal("cs_n", Pins("AE21"), IOStandard("SSTL15")), - Subsignal("dm", Pins( - "AA28 AA27 AE28 AH30 AB18 AJ19 AD14 AK16"), - IOStandard("SSTL15")), - Subsignal("dq", Pins( - "W29 Y29 AB30 AB29 W28 W26 Y28 AB28 AA25 AD27 AB24 AC24 Y26 Y25 AA26 AC26" + \ - "AD29 AE30 AE29 AF30 AD28 AC27 AF28 AF27 AG30 AG29 AH29 AJ29 AK30 AK29 AK28 AG27" + \ - "AD18 AD19 AA18 Y18 AE18 Y19 AB17 AA17 AH20 AH19 AG19 AF18 AJ18 AK18 AJ17 AJ16" + \ - "AF16 AE16 AE15 AF15 AC15 AB15 AC14 AB14 AH17 AH16 AK14 AJ14 AF17 AG17 AH15 AH14"), - IOStandard("SSTL15_T_DCI")), - Subsignal("dqs_p", Pins("Y30 AB25 AC29 AJ27 AC17 AK19 AC16 AG14"), - IOStandard("DIFF_SSTL15")), - Subsignal("dqs_n", Pins("AA30 AC25 AC30 AJ28 AD17 AK20 AD16 AG15"), - IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("AA22"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("AA23"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("AB22"), IOStandard("SSTL15")), - Subsignal("odt", Pins("AH24"), IOStandard("SSTL15")), - Subsignal("reset_n", Pins("Y21"), IOStandard("LVCMOS15")), - Misc("SLEW=FAST"), - Misc("VCCAUX_IO=NORMAL") - ), + # DDR3 SDRAM near SFP ports + ("ddram", 0, + Subsignal("a", Pins( + "F28 E29 F26 D29 B29 C30 A30 B28 C29 B30 E30 E26 A28 H29 F25"), + IOStandard("SSTL15")), + Subsignal("ba", Pins("F30 G28 E28"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("H27"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("G30"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("G29"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("H30"), IOStandard("SSTL15")), + Subsignal("dm", Pins( + "B22 E19 F22 K19 M23 P18 P26 N29"), + IOStandard("SSTL15")), + Subsignal("dq", Pins( + "A21 A22 A23 B23 B19 C19 A20 B20 C21 D21 C22 D22 E18 D18 E20 E21 " + \ + "G18 F18 G20 F20 H20 G22 G23 F23 L18 J18 J19 K20 J22 H22 K23 J23 " + \ + "N24 N22 P24 P23 L20 M22 M24 N25 M17 N19 N17 P17 N20 N21 P21 P19 " + \ + "K26 K25 L26 L25 M25 N26 P28 P27 L30 M29 P29 R29 K28 K29 K30 M28 "), + IOStandard("SSTL15")), + Subsignal("dqs_p", Pins("B18 E23 H19 K21 L23 M18 N27 N30"), + IOStandard("DIFF_SSTL15")), + Subsignal("dqs_n", Pins("A18 D23 G19 J21 K24 M19 M27 M30"), + IOStandard("DIFF_SSTL15")), + Subsignal("clk_p", Pins("J26"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_n", Pins("J27"), IOStandard("DIFF_SSTL15")), + Subsignal("cke", Pins("G25"), IOStandard("SSTL15")), + Subsignal("odt", Pins("J28"), IOStandard("SSTL15")), + Subsignal("reset_n", Pins("F27"), IOStandard("LVCMOS15")), + Misc("SLEW=FAST"), + ), - # Sata - ("sata", 0, - Subsignal("rx_p", Pins("C12")), - Subsignal("rx_n", Pins("C11")), - Subsignal("tx_p", Pins("A12")), - Subsignal("tx_n", Pins("A11")), - IOStandard("LVDS"), - ), - ("sata", 1, - Subsignal("rx_p", Pins("E12")), - Subsignal("rx_n", Pins("E11")), - Subsignal("tx_p", Pins("B10")), - Subsignal("tx_n", Pins("B9")), - IOStandard("LVDS"), - ), + # DDR3 SDRAM near power supply + ("ddram", 1, + Subsignal("a", Pins( + "AG22 AJ23 AF22 AJ26 AG23 AD23 AF23 AJ24 AE23 AB23 AJ22 AK25 AD21 AD22 AK24"), + IOStandard("SSTL15")), + Subsignal("ba", Pins("AK23 AF21 AC21"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("AF20"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("AK21"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("AJ21"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("AE21"), IOStandard("SSTL15")), + Subsignal("dm", Pins( + "AA28 AA27 AE28 AH30 AB18 AJ19 AD14 AK16"), + IOStandard("SSTL15")), + Subsignal("dq", Pins( + "W29 Y29 AB30 AB29 W28 W26 Y28 AB28 AA25 AD27 AB24 AC24 Y26 Y25 AA26 AC26 " + \ + "AD29 AE30 AE29 AF30 AD28 AC27 AF28 AF27 AG30 AG29 AH29 AJ29 AK30 AK29 AK28 AG27 " + \ + "AD18 AD19 AA18 Y18 AE18 Y19 AB17 AA17 AH20 AH19 AG19 AF18 AJ18 AK18 AJ17 AJ16 " + \ + "AF16 AE16 AE15 AF15 AC15 AB15 AC14 AB14 AH17 AH16 AK14 AJ14 AF17 AG17 AH15 AH14 "), + IOStandard("SSTL15")), + Subsignal("dqs_p", Pins("Y30 AB25 AC29 AJ27 AC17 AK19 AC16 AG14"), + IOStandard("DIFF_SSTL15")), + Subsignal("dqs_n", Pins("AA30 AC25 AC30 AJ28 AD17 AK20 AD16 AG15"), + IOStandard("DIFF_SSTL15")), + Subsignal("clk_p", Pins("AA22"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_n", Pins("AA23"), IOStandard("DIFF_SSTL15")), + Subsignal("cke", Pins("AB22"), IOStandard("SSTL15")), + Subsignal("odt", Pins("AG20"), IOStandard("SSTL15")), + Subsignal("reset_n", Pins("Y21"), IOStandard("LVCMOS15")), + Misc("SLEW=FAST"), + ), - # PCIe - ("pcie_x1", 0, - Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")), - Subsignal("clk_p", Pins("T6")), - Subsignal("clk_n", Pins("T5")), - Subsignal("rx_p", Pins("P6")), - Subsignal("rx_n", Pins("P5")), - Subsignal("tx_p", Pins("N4")), - Subsignal("tx_n", Pins("N3")) - ), - ("pcie_x2", 0, - Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")), - Subsignal("clk_p", Pins("T6")), - Subsignal("clk_n", Pins("T5")), - Subsignal("rx_p", Pins("")), - Subsignal("rx_p", Pins("P6 R4")), - Subsignal("rx_n", Pins("P5 R3")), - Subsignal("tx_p", Pins("N4 P2")), - Subsignal("tx_n", Pins("N3 P1")) - ), - ("pcie_x4", 0, - Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")), - Subsignal("clk_p", Pins("T6")), - Subsignal("clk_n", Pins("T5")), - Subsignal("rx_p", Pins("P6 R4 U4 V6")), - Subsignal("rx_n", Pins("P5 R3 U3 V5")), - Subsignal("tx_p", Pins("N4 P2 T2 V2")), - Subsignal("tx_n", Pins("N3 P1 T1 V1")) - ), - ("pcie_x8", 0, - Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS33")), - Subsignal("clk_p", Pins("T6")), - Subsignal("clk_n", Pins("T5")), - Subsignal("rx_p", Pins("P6 R4 U4 V6 W4 Y6 AA4 AB6")), - Subsignal("rx_n", Pins("P5 R3 U3 V5 W3 Y5 AA3 AB5")), - Subsignal("tx_p", Pins("N4 P2 T2 V2 Y2 AB2 AD2 AF2")), - Subsignal("tx_n", Pins("N3 P1 T1 V1 Y1 AB1 AD1 AF1")) - ), + # Sata + ("sata", 0, + Subsignal("rx_p", Pins("C12")), + Subsignal("rx_n", Pins("C11")), + Subsignal("tx_p", Pins("A12")), + Subsignal("tx_n", Pins("A11")), + IOStandard("LVDS"), + ), + ("sata", 1, + Subsignal("rx_p", Pins("E12")), + Subsignal("rx_n", Pins("E11")), + Subsignal("tx_p", Pins("B10")), + Subsignal("tx_n", Pins("B9")), + IOStandard("LVDS"), + ), + + # PCIe + ("pcie_x1", 0, + Subsignal("rst_n", Pins("W21"), io_standard), + Subsignal("clk_p", Pins("T6")), + Subsignal("clk_n", Pins("T5")), + Subsignal("rx_p", Pins("P6")), + Subsignal("rx_n", Pins("P5")), + Subsignal("tx_p", Pins("N4")), + Subsignal("tx_n", Pins("N3")) + ), + ("pcie_x2", 0, + Subsignal("rst_n", Pins("W21"), io_standard), + Subsignal("clk_p", Pins("T6")), + Subsignal("clk_n", Pins("T5")), + Subsignal("rx_p", Pins("")), + Subsignal("rx_p", Pins("P6 R4")), + Subsignal("rx_n", Pins("P5 R3")), + Subsignal("tx_p", Pins("N4 P2")), + Subsignal("tx_n", Pins("N3 P1")) + ), + ("pcie_x4", 0, + Subsignal("rst_n", Pins("W21"), io_standard), + Subsignal("clk_p", Pins("T6")), + Subsignal("clk_n", Pins("T5")), + Subsignal("rx_p", Pins("P6 R4 U4 V6")), + Subsignal("rx_n", Pins("P5 R3 U3 V5")), + Subsignal("tx_p", Pins("N4 P2 T2 V2")), + Subsignal("tx_n", Pins("N3 P1 T1 V1")) + ), + ("pcie_x8", 0, + Subsignal("rst_n", Pins("W21"), io_standard), + Subsignal("clk_p", Pins("T6")), + Subsignal("clk_n", Pins("T5")), + Subsignal("rx_p", Pins("P6 R4 U4 V6 W4 Y6 AA4 AB6")), + Subsignal("rx_n", Pins("P5 R3 U3 V5 W3 Y5 AA3 AB5")), + Subsignal("tx_p", Pins("N4 P2 T2 V2 Y2 AB2 AD2 AF2")), + Subsignal("tx_n", Pins("N3 P1 T1 V1 Y1 AB1 AD1 AF1")) + ), - # SFP - ("sfp_a", 0, # SFP A - Subsignal("txp", Pins("A8")), - Subsignal("txn", Pins("A7")), - Subsignal("rxp", Pins("D10")), - Subsignal("rxn", Pins("D9")), - Subsignal("sda", Pins("C15")), - Subsignal("scl", Pins("A15")), - ), - ("sfp_a_tx", 0, # SFP A - Subsignal("p", Pins("A8")), - Subsignal("n", Pins("A7")) - ), - ("sfp_a_rx", 0, # SFP A - Subsignal("p", Pins("D10")), - Subsignal("n", Pins("D9")) - ), - ("sfp_b", 0, # SFP B - Subsignal("txp", Pins("C8")), - Subsignal("txn", Pins("C7")), - Subsignal("rxp", Pins("F10")), - Subsignal("rxn", Pins("F9")), - Subsignal("sda", Pins("C14")), - Subsignal("scl", Pins("B14")), - ), - ("sfp_b_tx", 0, # SFP B - Subsignal("p", Pins("C8")), - Subsignal("n", Pins("C7")) - ), - ("sfp_b_rx", 0, # SFP B - Subsignal("p", Pins("F10")), - Subsignal("n", Pins("F9")) - ), -] + # SFP A + ("sfp_a", 0, + Subsignal("txp", Pins("A8")), + Subsignal("txn", Pins("A7")), + Subsignal("rxp", Pins("D10")), + Subsignal("rxn", Pins("D9")), + Subsignal("sda", Pins("C15"), io_standard), + Subsignal("scl", Pins("A15"), io_standard), + ), + ("sfp_a_tx", 0, + Subsignal("p", Pins("A8")), + Subsignal("n", Pins("A7")) + ), + ("sfp_a_rx", 0, + Subsignal("p", Pins("D10")), + Subsignal("n", Pins("D9")) + ), + ("sfp_a_tx_disable_n", 0, Pins("Y20"), io_standard), + + # SFP B + ("sfp_b", 0, + Subsignal("txp", Pins("C8")), + Subsignal("txn", Pins("C7")), + Subsignal("rxp", Pins("F10")), + Subsignal("rxn", Pins("F9")), + Subsignal("sda", Pins("C14"), io_standard), + Subsignal("scl", Pins("B14"), io_standard), + ), + ("sfp_b_tx", 0, + Subsignal("p", Pins("C8")), + Subsignal("n", Pins("C7")) + ), + ("sfp_b_rx", 0, + Subsignal("p", Pins("F10")), + Subsignal("n", Pins("F9")) + ), + ("sfp_b_tx_disable_n", 0, Pins("D14"), io_standard), + ] + + return _io # Connectors --------------------------------------------------------------------------------------- @@ -311,13 +317,15 @@ class Platform(XilinxPlatform): default_clk_name = "diffclk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7k420t-ffg901-2", _io, _connectors, toolchain="ISE") - self.add_platform_command(""" - set_property CONFIG_VOLTAGE 3.3 [current_design] - set_property CFGBVS VCCO [current_design] - """) + def __init__(self, io_voltage="3.3V"): + assert io_voltage in ["2.5V", "3.3V"], "io_voltage must be '2.5V' or '3.3V' acording to the board jumper" + io_standard = IOStandard("LVCMOS33") if io_voltage == "3.3V" else IOStandard("LVCMOS25") + _io = _get_io(io_standard) + + XilinxPlatform.__init__(self, "xc7k420t-ffg901-2", _io, _connectors, toolchain="ise") self.toolchain.bitstream_commands = [ + "set_property CONFIG_VOLTAGE 3.3 [current_design]", + "set_property CFGBVS VCCO [current_design]", "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", "set_property BITSTREAM.CONFIG.CCLK_TRISTATE TRUE [current_design]", diff --git a/litex_boards/targets/hpcstore_xc7k420t.py b/litex_boards/targets/hpcstore_xc7k420t.py index d99be11..2997589 100755 --- a/litex_boards/targets/hpcstore_xc7k420t.py +++ b/litex_boards/targets/hpcstore_xc7k420t.py @@ -17,7 +17,7 @@ import os from migen import * -from litex_boards.platforms import aliexpress_stlv7325 +from litex_boards.platforms import hpcstore_xc7k420t from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -25,7 +25,7 @@ from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litex.soc.cores.bitbang import I2CMaster -from litedram.modules import MT8JTF12864 +from litedram.modules import K4B1G0446F from litedram.phy import s7ddrphy from litepcie.phy.s7pciephy import S7PCIEPHY @@ -36,9 +36,10 @@ from litepcie.software import generate_litepcie_software class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.rst = Signal() - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain() - self.clock_domains.cd_idelay = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain() + self.clock_domains.cd_sys4x_dqs = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # @@ -47,12 +48,13 @@ class _CRG(Module): rst_n = platform.request("cpu_reset_n") # PLL. - self.submodules.pll = pll = S7MMCM(speedgrade=-2) + self.submodules.pll = pll = S7PLL(speedgrade=-2) self.comb += pll.reset.eq(~rst_n | self.rst) pll.register_clkin(clk100, 100e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_idelay, 200e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) + pll.create_clkout(self.cd_idelay, 200e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) @@ -61,11 +63,12 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), + io_voltage="3.3V", with_led_chaser = True, with_pcie = False, with_sata = False, **kwargs): - platform = aliexpress_stlv7325.Platform() + platform = hpcstore_xc7k420t.Platform(io_voltage) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -75,14 +78,16 @@ class BaseSoC(SoCCore): # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), + # we need to use A7DDRPHY instead of K7DDRPHY, because the 420T has no ODELAYE2 + self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram", 0), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq, + iodelay_clk_freq = 200e6 ) self.add_sdram("sdram", phy = self.ddrphy, - module = MT8JTF12864(sys_clk_freq, "1:4"), + module = K4B1G0446F(sys_clk_freq, "1:4", "800"), l2_cache_size = kwargs.get("l2_size", 8192), ) @@ -131,10 +136,10 @@ def main(): from litex.soc.integration.soc import LiteXSoCArgumentParser parser = LiteXSoCArgumentParser(description="LiteX SoC on AliExpress HPC Store XC7K420T") target_group = parser.add_argument_group(title="Target options") - target_group.add_argument("--build", action="store_true", help="Build design.") - target_group.add_argument("--load", action="store_true", help="Load bitstream.") - target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") - ethopts = target_group.add_mutually_exclusive_group() + target_group.add_argument("--build", action="store_true", help="Build design.") + target_group.add_argument("--load", action="store_true", help="Load bitstream.") + target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") + target_group.add_argument("--io-voltage", default="3.3V", help="IO voltage chosen by Jumper J3. Can be: '3.3V' or '2.5V'") target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.") target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.") target_group.add_argument("--with-sata", action="store_true", help="Enable SATA support.") @@ -144,6 +149,7 @@ def main(): soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), + io_voltage = args.io_voltage, with_pcie = args.with_pcie, with_sata = args.with_sata, **soc_core_argdict(args) From 006b54e7eaefbd6e99d119f440edc1b5378a04f5 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Sat, 14 May 2022 21:34:23 +0700 Subject: [PATCH 3/4] Get 3 DDR modules working with Vivado --- litex_boards/platforms/hpcstore_xc7k420t.py | 21 +++++++++++++-------- litex_boards/targets/hpcstore_xc7k420t.py | 10 ++++++---- 2 files changed, 19 insertions(+), 12 deletions(-) diff --git a/litex_boards/platforms/hpcstore_xc7k420t.py b/litex_boards/platforms/hpcstore_xc7k420t.py index 4b1970a..d57976f 100644 --- a/litex_boards/platforms/hpcstore_xc7k420t.py +++ b/litex_boards/platforms/hpcstore_xc7k420t.py @@ -74,8 +74,8 @@ def _get_io(io_standard): IOStandard("DIFF_SSTL15")), Subsignal("dqs_n", Pins("A18 D23 G19 J21 K24 M19 M27 M30"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("J26"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("J27"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_p", Pins("J26"), IOStandard("DIFF_SSTL15"), Misc("IO_BUFFER_TYPE=NONE")), + Subsignal("clk_n", Pins("J27"), IOStandard("DIFF_SSTL15"), Misc("IO_BUFFER_TYPE=NONE")), Subsignal("cke", Pins("G25"), IOStandard("SSTL15")), Subsignal("odt", Pins("J28"), IOStandard("SSTL15")), Subsignal("reset_n", Pins("F27"), IOStandard("LVCMOS15")), @@ -119,14 +119,12 @@ def _get_io(io_standard): Subsignal("rx_n", Pins("C11")), Subsignal("tx_p", Pins("A12")), Subsignal("tx_n", Pins("A11")), - IOStandard("LVDS"), ), ("sata", 1, Subsignal("rx_p", Pins("E12")), Subsignal("rx_n", Pins("E11")), Subsignal("tx_p", Pins("B10")), Subsignal("tx_n", Pins("B9")), - IOStandard("LVDS"), ), # PCIe @@ -314,7 +312,7 @@ _connectors = [ # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): - default_clk_name = "diffclk100" + default_clk_name = "clk100" default_clk_period = 1e9/100e6 def __init__(self, io_voltage="3.3V"): @@ -322,10 +320,17 @@ class Platform(XilinxPlatform): io_standard = IOStandard("LVCMOS33") if io_voltage == "3.3V" else IOStandard("LVCMOS25") _io = _get_io(io_standard) - XilinxPlatform.__init__(self, "xc7k420t-ffg901-2", _io, _connectors, toolchain="ise") + XilinxPlatform.__init__(self, "xc7k420t-ffg901-2", _io, _connectors, toolchain="vivado") + self.add_platform_command(""" + set_property CONFIG_VOLTAGE 3.3 [current_design] + set_property CFGBVS VCCO [current_design]""") + self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 11]") + self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 12]") + self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 13]") + self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 16]") + self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 17]") + self.toolchain.bitstream_commands = [ - "set_property CONFIG_VOLTAGE 3.3 [current_design]", - "set_property CFGBVS VCCO [current_design]", "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", "set_property BITSTREAM.CONFIG.CCLK_TRISTATE TRUE [current_design]", diff --git a/litex_boards/targets/hpcstore_xc7k420t.py b/litex_boards/targets/hpcstore_xc7k420t.py index 2997589..ba85085 100755 --- a/litex_boards/targets/hpcstore_xc7k420t.py +++ b/litex_boards/targets/hpcstore_xc7k420t.py @@ -25,8 +25,9 @@ from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litex.soc.cores.bitbang import I2CMaster -from litedram.modules import K4B1G0446F from litedram.phy import s7ddrphy +from litedram.common import PHYPadsReducer +from litedram.modules import K4B1G0446F from litepcie.phy.s7pciephy import S7PCIEPHY from litepcie.software import generate_litepcie_software @@ -44,7 +45,7 @@ class _CRG(Module): # # # # Clk/Rst. - clk100 = platform.request("diffclk100") + clk100 = platform.request("clk100") rst_n = platform.request("cpu_reset_n") # PLL. @@ -79,7 +80,8 @@ class BaseSoC(SoCCore): # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: # we need to use A7DDRPHY instead of K7DDRPHY, because the 420T has no ODELAYE2 - self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram", 0), + self.submodules.ddrphy = s7ddrphy.A7DDRPHY( + pads = PHYPadsReducer(platform.request("ddram", 0), [0, 1, 2]), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq, @@ -87,7 +89,7 @@ class BaseSoC(SoCCore): ) self.add_sdram("sdram", phy = self.ddrphy, - module = K4B1G0446F(sys_clk_freq, "1:4", "800"), + module = K4B1G0446F(sys_clk_freq, "1:4", "1066"), l2_cache_size = kwargs.get("l2_size", 8192), ) From c5d292c7f95c9ea359c0b757f1613c9f32364dc4 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Mon, 16 May 2022 12:33:04 +0700 Subject: [PATCH 4/4] Get 4 DDR modules working with Vivado --- litex_boards/targets/hpcstore_xc7k420t.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/litex_boards/targets/hpcstore_xc7k420t.py b/litex_boards/targets/hpcstore_xc7k420t.py index ba85085..d301c87 100755 --- a/litex_boards/targets/hpcstore_xc7k420t.py +++ b/litex_boards/targets/hpcstore_xc7k420t.py @@ -54,7 +54,7 @@ class _CRG(Module): pll.register_clkin(clk100, 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) + pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=120) pll.create_clkout(self.cd_idelay, 200e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. @@ -81,7 +81,8 @@ class BaseSoC(SoCCore): if not self.integrated_main_ram_size: # we need to use A7DDRPHY instead of K7DDRPHY, because the 420T has no ODELAYE2 self.submodules.ddrphy = s7ddrphy.A7DDRPHY( - pads = PHYPadsReducer(platform.request("ddram", 0), [0, 1, 2]), + pads = PHYPadsReducer(platform.request("ddram", 0), [0, 1, 2, 3]), + #pads = platform.request("ddram", 0), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq, @@ -89,7 +90,7 @@ class BaseSoC(SoCCore): ) self.add_sdram("sdram", phy = self.ddrphy, - module = K4B1G0446F(sys_clk_freq, "1:4", "1066"), + module = K4B1G0446F(sys_clk_freq, "1:4", "800"), l2_cache_size = kwargs.get("l2_size", 8192), )