From 6567af6f49ebd7be39e30da99b1c0cdfa83d6114 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Sat, 22 Jan 2022 18:50:12 -0800 Subject: [PATCH] Digilent CMOD A7: add flash support. Add both "--flash" and "--with-spi-flash"; tested on board. 4MB flash mapped at 0x00400000. Signed-off-by: Tim Callahan --- litex_boards/platforms/digilent_cmod_a7.py | 18 ++++++++++++++++++ litex_boards/targets/digilent_cmod_a7.py | 15 +++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/litex_boards/platforms/digilent_cmod_a7.py b/litex_boards/platforms/digilent_cmod_a7.py index c6bb8b4..964bdc0 100644 --- a/litex_boards/platforms/digilent_cmod_a7.py +++ b/litex_boards/platforms/digilent_cmod_a7.py @@ -51,6 +51,24 @@ _io = [ Subsignal("cen", Pins("N19"), IOStandard("LVCMOS33")), Misc("SLEW=FAST"), ), + + # SPIFlash + ("spiflash", 0, + Subsignal("cs_n", Pins("K19")), + Subsignal("clk", Pins("E19")), + Subsignal("mosi", Pins("D18")), + Subsignal("miso", Pins("D19")), + Subsignal("wp", Pins("G18")), + Subsignal("hold", Pins("F18")), + IOStandard("LVCMOS33"), + ), + ("spiflash4x", 0, + Subsignal("cs_n", Pins("K19")), + Subsignal("clk", Pins("E19")), + Subsignal("dq", Pins("D18 D19 G18 F18")), + IOStandard("LVCMOS33") + ), + ] # Connectors --------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py index 92d9ae2..db44667 100755 --- a/litex_boards/targets/digilent_cmod_a7.py +++ b/litex_boards/targets/digilent_cmod_a7.py @@ -109,6 +109,7 @@ class BaseSoC(SoCCore): toolchain = "vivado", sys_clk_freq = int(100e6), with_led_chaser = True, + with_spi_flash = False, **kwargs): platform = digilent_cmod_a7.Platform(variant=variant, toolchain=toolchain) @@ -129,6 +130,12 @@ class BaseSoC(SoCCore): pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) + # SPI Flash -------------------------------------------------------------------------------- + if with_spi_flash: + from litespi.modules import MX25U3235F + from litespi.opcodes import SpiNorFlashOpCodes as Codes + self.add_spi_flash(mode="4x", module=MX25U3235F(Codes.READ_1_1_4), with_master=True) + # Build -------------------------------------------------------------------------------------------- def main(): @@ -136,8 +143,11 @@ def main(): parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).") parser.add_argument("--build", action="store_true", help="Build bitstream.") parser.add_argument("--load", action="store_true", help="Load bitstream.") + parser.add_argument("--flash", action="store_true", help="Flash bitstream.") parser.add_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).") parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.") + parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).") + builder_args(parser) soc_core_args(parser) @@ -148,6 +158,7 @@ def main(): variant = args.variant, toolchain = args.toolchain, sys_clk_freq = int(float(args.sys_clk_freq)), + with_spi_flash = args.with_spi_flash, **soc_core_argdict(args) ) @@ -162,5 +173,9 @@ def main(): prog = soc.platform.create_programmer() prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) + if args.flash: + prog = soc.platform.create_programmer() + prog.flash(0, os.path.join(builder.gateware_dir, soc.build_name + ".bit")) + if __name__ == "__main__": main()