From 764f64ff1ec85180053bec5473528aa35e318d2e Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 4 Jan 2023 12:02:11 +0100 Subject: [PATCH] nx_vip: Add missing 'origin' to SRAM SocRegions Signed-off-by: gatecat --- litex_boards/targets/lattice_crosslink_nx_vip.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/lattice_crosslink_nx_vip.py b/litex_boards/targets/lattice_crosslink_nx_vip.py index 37f3622..7ffee5e 100755 --- a/litex_boards/targets/lattice_crosslink_nx_vip.py +++ b/litex_boards/targets/lattice_crosslink_nx_vip.py @@ -84,13 +84,15 @@ class BaseSoC(SoCCore): # 128KB LRAM (used as SRAM) ------------------------------------------------------------ size = 128*kB self.spram = NXLRAM(32, size) - self.bus.add_slave("sram", slave=self.spram.bus, region=SoCRegion(size=size)) + self.bus.add_slave("sram", slave=self.spram.bus, region=SoCRegion(origin=self.mem_map["sram"], + size=size)) else: # Use HyperRAM generic PHY as SRAM ----------------------------------------------------- size = 8*1024*kB hr_pads = platform.request("hyperram", int(hyperram)) self.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq) - self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(size=size)) + self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["sram"], + size=size)) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: