From 666ef9dad3cc330e6bce90c063f4e5d6f3c1e70e Mon Sep 17 00:00:00 2001
From: Ilia Sergachev <ilia.sergachev@protonmail.ch>
Date: Mon, 29 Nov 2021 11:46:32 +0100
Subject: [PATCH] sipeed_tang_nano_4k: use minimal vexriscv variant to fit into
 number of BSRAMs

---
 litex_boards/targets/sipeed_tang_nano_4k.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py
index d892f5c..df31fa3 100755
--- a/litex_boards/targets/sipeed_tang_nano_4k.py
+++ b/litex_boards/targets/sipeed_tang_nano_4k.py
@@ -72,6 +72,9 @@ class BaseSoC(SoCCore):
         kwargs["integrated_rom_size"] = 0
         kwargs["cpu_reset_address"]   = self.mem_map["spiflash"] + 0
 
+        kwargs["cpu_type"] = 'vexriscv'
+        kwargs["cpu_variant"] = 'minimal'
+
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
             ident         = "LiteX SoC on Tang Nano 4K",