diff --git a/litex_boards/platforms/digilent_arty_z7.py b/litex_boards/platforms/digilent_arty_z7.py
index 9d70197..e1adc0b 100644
--- a/litex_boards/platforms/digilent_arty_z7.py
+++ b/litex_boards/platforms/digilent_arty_z7.py
@@ -2,8 +2,7 @@
 # License: BSD
 
 from litex.build.generic_platform import Pins, IOStandard, Subsignal
-from litex.build.xilinx import XilinxPlatform
-from litex.build.openfpgaloader import OpenFPGALoader
+from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -237,7 +236,7 @@ class Platform(XilinxPlatform):
         XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
 
     def create_programmer(self):
-        return OpenFPGALoader(self.board)
+        return VivadoProgrammer()
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
diff --git a/litex_boards/targets/digilent_arty_z7.py b/litex_boards/targets/digilent_arty_z7.py
index 5dc297d..e83033d 100755
--- a/litex_boards/targets/digilent_arty_z7.py
+++ b/litex_boards/targets/digilent_arty_z7.py
@@ -127,7 +127,7 @@ def main():
 
     if args.load:
         prog = soc.platform.create_programmer()
-        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
+        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"), device=1)
 
 if __name__ == "__main__":
     main()