From 68e045367769070d66d57e3a7ccdcacfd5fd598e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 21 Feb 2024 09:03:53 +0100 Subject: [PATCH] targets/digilent_arty: Move USB integrated to BaseSoC. --- litex_boards/targets/digilent_arty.py | 62 ++++++++++++++------------- 1 file changed, 32 insertions(+), 30 deletions(-) diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py index b86d64e..14c63f0 100755 --- a/litex_boards/targets/digilent_arty.py +++ b/litex_boards/targets/digilent_arty.py @@ -79,6 +79,7 @@ class BaseSoC(SoCCore): eth_ip = "192.168.1.50", remote_ip = None, eth_dynamic_ip = False, + with_usb = False, with_led_chaser = True, with_spi_flash = False, with_buttons = False, @@ -130,6 +131,36 @@ class BaseSoC(SoCCore): from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), rate="1:2", with_master=True) + # USB-OHCI --------------------------------------------------------------------------------- + if with_usb: + from litex.soc.cores.usb_ohci import USBOHCI + from litex.build.generic_platform import Subsignal, Pins, IOStandard + + self.crg.cd_usb = ClockDomain() + self.crg.pll.create_clkout(self.crg.cd_usb, 48e6, margin=0) + + # Machdyne PMOD (https://github.com/machdyne/usb_host_dual_socket_pmod) + _usb_pmod_ios = [ + ("usb_pmoda", 0, # USB1 (top socket) + Subsignal("dp", Pins("pmoda:2")), + Subsignal("dm", Pins("pmoda:3")), + IOStandard("LVCMOS33"), + ), + ("usb_pmoda", 1, # USB2 (bottom socket) + Subsignal("dp", Pins("pmoda:0")), + Subsignal("dm", Pins("pmoda:1")), + IOStandard("LVCMOS33"), + ) + ] + self.platform.add_extension(_usb_pmod_ios) + + self.submodules.usb_ohci = USBOHCI(self.platform, self.platform.request("usb_pmoda", 0), usb_clk_freq=int(48e6)) + self.mem_map["usb_ohci"] = 0xc0000000 + self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False)) # FIXME: Mapping. + self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma) + + self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt) + # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.leds = LedChaser( @@ -192,6 +223,7 @@ def main(): eth_ip = args.eth_ip, remote_ip = args.remote_ip, eth_dynamic_ip = args.eth_dynamic_ip, + with_usb = args.with_usb, with_spi_flash = args.with_spi_flash, with_pmod_gpio = args.with_pmod_gpio, **parser.soc_argdict @@ -205,36 +237,6 @@ def main(): if args.with_sdcard: soc.add_sdcard() - # USB Host --------------------------------------------------------------------------------- - if args.with_usb: - from litex.soc.cores.usb_ohci import USBOHCI - from litex.build.generic_platform import Subsignal, Pins, IOStandard - - soc.crg.clock_domains.cd_usb = ClockDomain() - soc.crg.pll.create_clkout(soc.crg.cd_usb, 48e6, margin=0) - - # Machdyne PMOD (https://github.com/machdyne/usb_host_dual_socket_pmod) - _usb_pmod_ios = [ - ("usb_pmoda", 0, # USB1 (top socket) - Subsignal("dp", Pins("pmoda:2")), - Subsignal("dm", Pins("pmoda:3")), - IOStandard("LVCMOS33"), - ), - ("usb_pmoda", 1, # USB2 (bottom socket) - Subsignal("dp", Pins("pmoda:0")), - Subsignal("dm", Pins("pmoda:1")), - IOStandard("LVCMOS33"), - ) - ] - soc.platform.add_extension(_usb_pmod_ios) - soc.submodules.usb_ohci = USBOHCI(soc.platform, soc.platform.request("usb_pmoda", 0), usb_clk_freq=int(48e6)) - soc.mem_map["usb_ohci"] = 0xc0000000 - soc.bus.add_slave("usb_ohci_ctrl", soc.usb_ohci.wb_ctrl, region=SoCRegion(origin=soc.mem_map["usb_ohci"], size=0x100000, cached=False)) # FIXME: Mapping. - soc.dma_bus.add_master("usb_ohci_dma", master=soc.usb_ohci.wb_dma) - - soc.comb += soc.cpu.interrupt[16].eq(soc.usb_ohci.interrupt) - - builder = Builder(soc, **parser.builder_argdict) if args.build: builder.build(**parser.toolchain_argdict)