From bccbd9552610e09a3774a6896dd855dcaeab6e06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bastian=20L=C3=B6her?= Date: Sun, 16 Jan 2022 11:31:08 +0100 Subject: [PATCH 1/3] digilent_cmod_a7: Propagate variant and toolchain --- litex_boards/platforms/digilent_cmod_a7.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/litex_boards/platforms/digilent_cmod_a7.py b/litex_boards/platforms/digilent_cmod_a7.py index 2b7de21..09e1280 100644 --- a/litex_boards/platforms/digilent_cmod_a7.py +++ b/litex_boards/platforms/digilent_cmod_a7.py @@ -63,8 +63,11 @@ class Platform(XilinxPlatform): default_clk_name = "clk12" default_clk_period = 1e9/12e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a35t-cpg236-1", _io, _connectors, toolchain="vivado") + def __init__(self, variant="a7-35", toolchain="vivado"): + device = { + "a7-35": "xc7a35t-cpg236-1" + }[variant] + XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain) def do_finalize(self,fragment): XilinxPlatform.do_finalize(self, fragment) From 1077e23e62ed5e5331b29ed2485d23fd646444d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bastian=20L=C3=B6her?= Date: Sun, 16 Jan 2022 11:58:14 +0100 Subject: [PATCH 2/3] digilent_cmod_a7: Also propagate here. --- litex_boards/targets/digilent_cmod_a7.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py index f43f22a..918aee2 100755 --- a/litex_boards/targets/digilent_cmod_a7.py +++ b/litex_boards/targets/digilent_cmod_a7.py @@ -121,7 +121,7 @@ class BaseSoC(SoCCore): with_mapped_flash=False, **kwargs): - platform = digilent_cmod_a7.Platform() + platform = digilent_cmod_a7.Platform(variant=variant, toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, @@ -144,7 +144,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7") + parser = argparse.ArgumentParser(description="LiteX SoC on CMOD A7") parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).") parser.add_argument("--build", action="store_true", help="Build bitstream.") parser.add_argument("--load", action="store_true", help="Load bitstream.") @@ -167,6 +167,7 @@ def main(): builder = Builder(soc, **builder_argd) builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {} + builder.build(**builder_kwargs, run=args.build) if __name__ == "__main__": From 38bff921b214045be21bb4332e0a9c4e4e6cfd5a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bastian=20L=C3=B6her?= Date: Sun, 16 Jan 2022 13:00:46 +0100 Subject: [PATCH 3/3] Fixup. --- litex_boards/platforms/digilent_cmod_a7.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex_boards/platforms/digilent_cmod_a7.py b/litex_boards/platforms/digilent_cmod_a7.py index 09e1280..476610c 100644 --- a/litex_boards/platforms/digilent_cmod_a7.py +++ b/litex_boards/platforms/digilent_cmod_a7.py @@ -65,10 +65,11 @@ class Platform(XilinxPlatform): def __init__(self, variant="a7-35", toolchain="vivado"): device = { - "a7-35": "xc7a35t-cpg236-1" + "a7-35": "xc7a35tcpg236-1" }[variant] XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain) def do_finalize(self,fragment): XilinxPlatform.do_finalize(self, fragment) + from litex.build.xilinx import symbiflow self.add_period_constraint(self.lookup_request("clk12", loose=True), self.default_clk_period)