From 6a5f2f59a69a48679e48716b8a3df5ffaf834a6a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 12 Jan 2021 18:56:58 +0100 Subject: [PATCH] targets/orangecrab: use new ECP5DDRPHY's cmd_delay to add extra delay on DDR3's Clock/Commands. This fixes https://github.com/enjoy-digital/litedram/issues/130 and has been tested at 48/64/96MHz on MT41K64M16 and MT41K512M16 variants. Also remove un-needed cd_sys2x_eb. --- litex_boards/targets/orangecrab.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index c988c5e..c777fdf 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -81,7 +81,6 @@ class _CRGSDRAM(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) - self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True) # # # @@ -183,6 +182,7 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = ECP5DDRPHY( pads = ddram_pads, sys_clk_freq = sys_clk_freq, + cmd_delay = 0 if sys_clk_freq > 64e6 else 100, dm_remapping = {0:1, 1:0}) self.ddrphy.settings.rtt_nom = "disabled" self.add_csr("ddrphy")