diff --git a/litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py
index ab8191d..7b339d3 100644
--- a/litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py
+++ b/litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py
@@ -162,7 +162,7 @@ def rgmii_ethernet_qse_ios(con):
             IOStandard("1.8_V_LVCMOS"),
         ),
         ("eth", 0,
-            Subsignal("rx_ctl",  Pins(f"{con}27")),
+            Subsignal("rx_ctl",  Pins(f"{con}:27")),
             Subsignal("rx_data", Pins(f"{con}:21 {con}:19 {con}:15 {con}:13")),
             Subsignal("tx_ctl",  Pins(f"{con}:20")),
             Subsignal("tx_data", Pins(f"{con}:16 {con}:14 {con}:10 {con}:8")),
diff --git a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py
index c8f189f..d117833 100755
--- a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py
+++ b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py
@@ -83,7 +83,7 @@ class BaseSoC(SoCCore):
                 pads               = platform.request("eth", eth_phy),
                 with_hw_init_reset = False)
             if with_ethernet:
-                self.add_ethernet(phy=self.ethphy, software_debug=False)
+                self.add_ethernet(phy=self.ethphy, software_debug=True)
             if with_etherbone:
                 self.add_etherbone(phy=self.ethphy)