From 6c31933e899b0e69615a3c042e4cdbf9d503e3b8 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 21 Mar 2020 21:40:45 +0100
Subject: [PATCH] targets: switch to add_etherbone method.

---
 litex_boards/targets/arty.py     | 47 +++++++-------------------------
 litex_boards/targets/genesys2.py | 18 +++++++++---
 2 files changed, 24 insertions(+), 41 deletions(-)

diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py
index fb5c8c1..aa20f60 100755
--- a/litex_boards/targets/arty.py
+++ b/litex_boards/targets/arty.py
@@ -19,8 +19,6 @@ from litedram.modules import MT41K128M16
 from litedram.phy import s7ddrphy
 
 from liteeth.phy.mii import LiteEthPHYMII
-from liteeth.core import LiteEthUDPIPCore
-from liteeth.frontend.etherbone import LiteEthEtherbone
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -52,7 +50,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs):
         platform = arty.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -87,34 +85,13 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
-# EtherboneSoC -------------------------------------------------------------------------------------
-
-class EtherboneSoC(BaseSoC):
-    def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
-
-        # Ethernet ---------------------------------------------------------------------------------
-        # phy
-        self.submodules.ethphy = LiteEthPHYMII(
-            clock_pads = self.platform.request("eth_clocks"),
-            pads       = self.platform.request("eth"))
-        self.add_csr("ethphy")
-        # core
-        self.submodules.ethcore = LiteEthUDPIPCore(
-            phy         = self.ethphy,
-            mac_address = 0x10e2d5000000,
-            ip_address  = "192.168.1.50",
-            clk_freq    = self.clk_freq)
-        # etherbone
-        self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234)
-        self.add_wb_master(self.etherbone.wishbone.bus)
-        # timing constraints
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6)
-        self.platform.add_false_path_constraints(
-            self.crg.cd_sys.clk,
-            self.ethphy.crg.cd_eth_rx.clk,
-            self.ethphy.crg.cd_eth_tx.clk)
+        # Etherbone --------------------------------------------------------------------------------
+        if with_etherbone:
+            self.submodules.ethphy = LiteEthPHYMII(
+                clock_pads = self.platform.request("eth_clocks"),
+                pads       = self.platform.request("eth"))
+            self.add_csr("ethphy")
+            self.add_etherbone(phy=self.ethphy)
 
 # Build --------------------------------------------------------------------------------------------
 
@@ -128,12 +105,8 @@ def main():
     args = parser.parse_args()
 
     assert not (args.with_ethernet and args.with_etherbone)
-    cls = BaseSoC
-    if args.with_ethernet:
-        cls = BaseSoC
-    if args.with_etherbone:
-        cls = EtherboneSoC
-    soc = cls(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
+    soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone,
+        **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build(**vivado_build_argdict(args))
 
diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py
index 4935382..0aa3330 100755
--- a/litex_boards/targets/genesys2.py
+++ b/litex_boards/targets/genesys2.py
@@ -41,7 +41,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, **kwargs):
         platform = genesys2.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -75,17 +75,27 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
+        # Etherbone --------------------------------------------------------------------------------
+        if with_etherbone:
+            self.submodules.ethphy = LiteEthPHYRGMII(
+                clock_pads = self.platform.request("eth_clocks"),
+                pads       = self.platform.request("eth"))
+            self.add_csr("ethphy")
+            self.add_etherbone(phy=self.ethphy)
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true",
-                        help="enable Ethernet support")
+    parser.add_argument("--with-ethernet",  action="store_true", help="enable Ethernet support")
+    parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support")
     args = parser.parse_args()
 
-    soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
+    assert not (args.with_ethernet and args.with_etherbone)
+    soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone,
+        **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()