From 6d07eda3c04a10fe270b7fefc8effe5a6cc8871c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 21 Feb 2024 10:06:49 +0100 Subject: [PATCH] targets/digilent_arty: Fix indent on with_usb. --- litex_boards/targets/digilent_arty.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py index 14c63f0..2a64bc9 100755 --- a/litex_boards/targets/digilent_arty.py +++ b/litex_boards/targets/digilent_arty.py @@ -152,14 +152,14 @@ class BaseSoC(SoCCore): IOStandard("LVCMOS33"), ) ] - self.platform.add_extension(_usb_pmod_ios) + self.platform.add_extension(_usb_pmod_ios) - self.submodules.usb_ohci = USBOHCI(self.platform, self.platform.request("usb_pmoda", 0), usb_clk_freq=int(48e6)) - self.mem_map["usb_ohci"] = 0xc0000000 - self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False)) # FIXME: Mapping. - self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma) + self.submodules.usb_ohci = USBOHCI(self.platform, self.platform.request("usb_pmoda", 0), usb_clk_freq=int(48e6)) + self.mem_map["usb_ohci"] = 0xc0000000 + self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False)) # FIXME: Mapping. + self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma) - self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt) + self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: