From 6d0a4c788e445cca02ded868849b79298317451a Mon Sep 17 00:00:00 2001 From: Adam Zeloof Date: Sat, 10 Sep 2022 17:45:57 +0100 Subject: [PATCH] Added DFU support to Butterstick --- litex_boards/platforms/gsd_butterstick.py | 12 +++++++++--- litex_boards/targets/gsd_butterstick.py | 4 ++-- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/litex_boards/platforms/gsd_butterstick.py b/litex_boards/platforms/gsd_butterstick.py index 05e270e..e159382 100644 --- a/litex_boards/platforms/gsd_butterstick.py +++ b/litex_boards/platforms/gsd_butterstick.py @@ -4,10 +4,11 @@ # Copyright (c) 2021 Greg Davill # Copyright (c) 2021 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause - + from litex.build.generic_platform import * from litex.build.lattice import LatticePlatform from litex.build.lattice.programmer import OpenOCDJTAGProgrammer +from litex.build.dfu import DFUProg # IOs ---------------------------------------------------------------------------------------------- @@ -194,8 +195,13 @@ class Platform(LatticePlatform): connectors = {"1.0": _connectors_r1_0}[revision] LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG381C", io, connectors, toolchain=toolchain, **kwargs) - def create_programmer(self): - return OpenOCDJTAGProgrammer("openocd_butterstick.cfg") + def create_programmer(self, load): + if load == "jtag": + return OpenOCDJTAGProgrammer("openocd_butterstick.cfg") + elif load == "dfu": + return DFUProg(vid="1209", pid="5af1", alt=0) + else: + print("Could not program board. "+load+" is not a valid argument. Please use 'jtag' or 'dfu'.") def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment) diff --git a/litex_boards/targets/gsd_butterstick.py b/litex_boards/targets/gsd_butterstick.py index 2e38282..d44fcad 100755 --- a/litex_boards/targets/gsd_butterstick.py +++ b/litex_boards/targets/gsd_butterstick.py @@ -155,7 +155,7 @@ def main(): parser = LiteXSoCArgumentParser(description="LiteX SoC on ButterStick") target_group = parser.add_argument_group(title="Target options") target_group.add_argument("--build", action="store_true", help="Build design.") - target_group.add_argument("--load", action="store_true", help="Load bitstream.") + target_group.add_argument("--load", default="jtag", help="Load bitstream (jtag or dfu).") target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).") target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") target_group.add_argument("--revision", default="1.0", help="Board Revision (1.0).") @@ -201,7 +201,7 @@ def main(): builder.build(**builder_kargs) if args.load: - prog = soc.platform.create_programmer() + prog = soc.platform.create_programmer(args.load) prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) if __name__ == "__main__":