From 6e31d12fa9daba462651bced299cae6cb7a11652 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 13 Jul 2021 19:39:27 +0200 Subject: [PATCH] trenz_tec0117: Avoid forcing CPU type (only force to lite variant when VexRiscv is selected=default). --- litex_boards/targets/trenz_tec0117.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/trenz_tec0117.py b/litex_boards/targets/trenz_tec0117.py index 443a0c1..205f72d 100755 --- a/litex_boards/targets/trenz_tec0117.py +++ b/litex_boards/targets/trenz_tec0117.py @@ -59,8 +59,8 @@ class BaseSoC(SoCCore): # Use custom default configuration to fit in LittleBee. kwargs["integrated_sram_size"] = 0x1000 kwargs["integrated_rom_size"] = 0x6000 - kwargs["cpu_type"] = "vexriscv" - kwargs["cpu_variant"] = "lite" + if kwargs.get("cpu_type", "vexriscv") == "vexriscv": + kwargs["cpu_variant"] = "lite" # Set CPU variant / reset address kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset