From 6e7c76b71e705ae79a89c05d0577aeac7799432c Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 5 Nov 2021 15:15:15 +0100
Subject: [PATCH] fairwaves_xtrx: Add clk60 (from USB PHY) as default Clk when
 no PCIe.

Fixes CI.
---
 litex_boards/platforms/fairwaves_xtrx.py |  4 ++++
 litex_boards/targets/fairwaves_xtrx.py   | 21 +++++++++++++--------
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/litex_boards/platforms/fairwaves_xtrx.py b/litex_boards/platforms/fairwaves_xtrx.py
index 0a1a2be..fecb80c 100644
--- a/litex_boards/platforms/fairwaves_xtrx.py
+++ b/litex_boards/platforms/fairwaves_xtrx.py
@@ -13,6 +13,9 @@ from litex.build.openocd import OpenOCD
 # IOs ----------------------------------------------------------------------------------------------
 
 _io = [
+    # Clk/Rst.
+    ("clk60", 0, Pins("C16"), IOStandard("LVCMOS25")),
+
     # Leds.
     ("user_led", 0, Pins("N18"),  IOStandard("LVCMOS25")),
 
@@ -51,3 +54,4 @@ class Platform(XilinxPlatform):
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk60", loose=True), 1e9/60e6)
diff --git a/litex_boards/targets/fairwaves_xtrx.py b/litex_boards/targets/fairwaves_xtrx.py
index 6895720..0d2f069 100755
--- a/litex_boards/targets/fairwaves_xtrx.py
+++ b/litex_boards/targets/fairwaves_xtrx.py
@@ -45,32 +45,37 @@ from litepcie.software import generate_litepcie_software
 
 class CRG(Module):
     def __init__(self, platform, sys_clk_freq, with_pcie=False):
-        assert sys_clk_freq == int(125e6)
         self.clock_domains.cd_sys = ClockDomain()
 
         # # #
 
-        self.comb += [
-            self.cd_sys.clk.eq(ClockSignal("pcie")),
-            self.cd_sys.rst.eq(ResetSignal("pcie")),
-
-        ]
+        if with_pcie:
+            assert sys_clk_freq == int(125e6)
+            self.comb += [
+                self.cd_sys.clk.eq(ClockSignal("pcie")),
+                self.cd_sys.rst.eq(ResetSignal("pcie")),
+            ]
+        else:
+            self.submodules.pll = pll = S7PLL(speedgrade=-2)
+            pll.register_clkin(platform.request("clk60"), 60e6)
+            pll.create_clkout(self.cd_sys, sys_clk_freq)
 
 # BaseSoC -----------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, with_led_chaser=True, **kwargs):
-        assert with_pcie
         platform = fairwaves_xtrx.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
+        if kwargs["uart_name"] == "serial":
+            kwargs["uart_name"] = "crossover"
         SoCCore.__init__(self, platform, sys_clk_freq,
             ident          = "LiteX SoC on Fairwaves XTRX",
             ident_version  = True,
             **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = CRG(platform, sys_clk_freq)
+        self.submodules.crg = CRG(platform, sys_clk_freq, with_pcie)
 
         # PCIe -------------------------------------------------------------------------------------
         if with_pcie: