diff --git a/litex_boards/platforms/c10lprefkit.py b/litex_boards/platforms/c10lprefkit.py
index eb1209a..b49a797 100644
--- a/litex_boards/platforms/c10lprefkit.py
+++ b/litex_boards/platforms/c10lprefkit.py
@@ -18,7 +18,6 @@ _io = [
     ("user_led", 3, Pins("C17"), IOStandard("3.3-V LVTTL")),
     ("user_led", 4, Pins("D18"), IOStandard("3.3-V LVTTL")),
 
-
     ("cpu_reset", 0, Pins("V15"), IOStandard("3.3-V LVTTL")),
 
     ("sw", 0, Pins("U10"), IOStandard("3.3-V LVTTL")),
diff --git a/litex_boards/platforms/camlink_4k.py b/litex_boards/platforms/camlink_4k.py
index cc9985f..ea541e4 100644
--- a/litex_boards/platforms/camlink_4k.py
+++ b/litex_boards/platforms/camlink_4k.py
@@ -15,8 +15,8 @@ from litex.build.lattice import LatticePlatform
 _io = [
     ("clk27", 0, Pins("B11"), IOStandard("LVCMOS25")),
 
-    ("led",   0, Pins("A6"), IOStandard("LVCMOS25")),
-    ("led",   1, Pins("A9"), IOStandard("LVCMOS25")),
+    ("user_led", 0, Pins("A6"), IOStandard("LVCMOS25")),
+    ("user_led", 1, Pins("A9"), IOStandard("LVCMOS25")),
 
     ("serial", 0,
         Subsignal("tx", Pins("A6")), # led0
diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py
index 26ce9a3..8ba2967 100755
--- a/litex_boards/targets/ac701.py
+++ b/litex_boards/targets/ac701.py
@@ -15,6 +15,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT8JTF12864
 from litedram.phy import s7ddrphy
@@ -111,6 +112,12 @@ class BaseSoC(SoCCore):
 
             self.add_ethernet(phy=self.ethphy)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(4)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on AC701")
diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py
index 6f1b092..d7c060e 100755
--- a/litex_boards/targets/acorn_cle_215.py
+++ b/litex_boards/targets/acorn_cle_215.py
@@ -24,6 +24,7 @@ from litex.soc.cores.clock import *
 from litex.soc.cores.dna import DNA
 from litex.soc.cores.xadc import XADC
 from litex.soc.cores.icap import ICAP
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT41K256M16
 from litedram.phy import s7ddrphy
@@ -33,8 +34,6 @@ from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
 from litepcie.frontend.dma import LitePCIeDMA
 from litepcie.frontend.wishbone import LitePCIeWishboneBridge
 
-
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class CRG(Module, AutoCSR):
@@ -159,6 +158,12 @@ class PCIeSoC(SoCCore):
             self.comb += self.pcie_msi.irqs[i].eq(v)
             self.add_constant(k + "_INTERRUPT", i)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(4)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
     def generate_software_headers(self):
         csr_header = get_csr_header(self.csr_regions, self.constants, with_access_functions=False)
         tools.write_to_file("csr.h", csr_header)
diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py
index 5cb54e5..8a396a1 100755
--- a/litex_boards/targets/aller.py
+++ b/litex_boards/targets/aller.py
@@ -25,6 +25,7 @@ from litex.soc.cores.clock import *
 from litex.soc.cores.dna import DNA
 from litex.soc.cores.xadc import XADC
 from litex.soc.cores.icap import ICAP
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT41J128M16
 from litedram.phy import s7ddrphy
@@ -34,8 +35,6 @@ from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
 from litepcie.frontend.dma import LitePCIeDMA
 from litepcie.frontend.wishbone import LitePCIeWishboneBridge
 
-
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class CRG(Module, AutoCSR):
@@ -159,6 +158,12 @@ class PCIeSoC(SoCCore):
             self.comb += self.pcie_msi.irqs[i].eq(v)
             self.add_constant(k + "_INTERRUPT", i)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(3)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
     def generate_software_headers(self):
         csr_header = get_csr_header(self.csr_regions, self.constants, with_access_functions=False)
         tools.write_to_file("csr.h", csr_header)
diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py
index 0613115..0450872 100755
--- a/litex_boards/targets/arty.py
+++ b/litex_boards/targets/arty.py
@@ -15,6 +15,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT41K128M16
 from litedram.phy import s7ddrphy
@@ -94,6 +95,12 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_etherbone(phy=self.ethphy)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(4)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/arty_s7.py b/litex_boards/targets/arty_s7.py
index acb9f8c..a2e27d2 100755
--- a/litex_boards/targets/arty_s7.py
+++ b/litex_boards/targets/arty_s7.py
@@ -16,6 +16,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT41K128M16
 from litedram.phy import s7ddrphy
@@ -73,6 +74,12 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(4)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py
index 9b3c10a..ac29a7a 100755
--- a/litex_boards/targets/c10lprefkit.py
+++ b/litex_boards/targets/c10lprefkit.py
@@ -16,6 +16,7 @@ from litex.soc.cores.clock import Cyclone10LPPLL
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT48LC16M16
 from litedram.phy import GENSDRPHY
@@ -89,6 +90,12 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(5)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py
index 7fd2977..7ec0480 100755
--- a/litex_boards/targets/camlink_4k.py
+++ b/litex_boards/targets/camlink_4k.py
@@ -95,6 +95,12 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(2)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py
index d17a1b3..114773d 100755
--- a/litex_boards/targets/de0nano.py
+++ b/litex_boards/targets/de0nano.py
@@ -17,6 +17,7 @@ from litex.soc.cores.clock import CycloneIVPLL
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import IS42S16160
 from litedram.phy import GENSDRPHY
@@ -67,6 +68,12 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py
index 6bd31c4..710c5ac 100755
--- a/litex_boards/targets/de10lite.py
+++ b/litex_boards/targets/de10lite.py
@@ -17,6 +17,7 @@ from litex.soc.cores.clock import Max10PLL
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import IS42S16320
 from litedram.phy import GENSDRPHY
@@ -71,6 +72,12 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(10)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # VGASoC -------------------------------------------------------------------------------------------
 
 class VGASoC(BaseSoC):
diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py
index d315a42..450f05a 100755
--- a/litex_boards/targets/de10nano.py
+++ b/litex_boards/targets/de10nano.py
@@ -17,6 +17,7 @@ from litex.soc.cores.clock import CycloneVPLL
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import AS4C16M16
 from litedram.phy import GENSDRPHY
@@ -55,6 +56,12 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(6)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # MiSTerSDRAMSoC -----------------------------------------------------------------------------------
 
 class MiSTerSDRAMSoC(SoCCore):
diff --git a/litex_boards/targets/ecp5_evn.py b/litex_boards/targets/ecp5_evn.py
index 80c4fde..fa8eca5 100755
--- a/litex_boards/targets/ecp5_evn.py
+++ b/litex_boards/targets/ecp5_evn.py
@@ -14,6 +14,7 @@ from litex_boards.platforms import ecp5_evn
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -51,6 +52,12 @@ class BaseSoC(SoCCore):
         crg = _CRG(platform, sys_clk_freq, x5_clk_freq)
         self.submodules.crg = crg
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py
index 57fe66a..d0c8c9a 100755
--- a/litex_boards/targets/genesys2.py
+++ b/litex_boards/targets/genesys2.py
@@ -14,6 +14,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT41J256M16
 from litedram.phy import s7ddrphy
@@ -85,6 +86,12 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_etherbone(phy=self.ethphy)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py
index 5434faf..3bb2157 100755
--- a/litex_boards/targets/kc705.py
+++ b/litex_boards/targets/kc705.py
@@ -16,6 +16,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT8JTF12864
 from litedram.phy import s7ddrphy
@@ -80,6 +81,12 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py
index ec8f59e..6c8a945 100755
--- a/litex_boards/targets/kcu105.py
+++ b/litex_boards/targets/kcu105.py
@@ -14,6 +14,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import EDY4016A
 from litedram.phy import usddrphy
@@ -88,6 +89,12 @@ class BaseSoC(SoCCore):
             self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
             self.add_ethernet(phy=self.ethphy)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/kx2.py b/litex_boards/targets/kx2.py
index 595d311..29b321c 100755
--- a/litex_boards/targets/kx2.py
+++ b/litex_boards/targets/kx2.py
@@ -14,11 +14,11 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import H5TC4G63CFR
 from litedram.phy import s7ddrphy
 
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
@@ -69,6 +69,12 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(4)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py
index 76fb4dd..bd2bc9c 100755
--- a/litex_boards/targets/linsn_rv901t.py
+++ b/litex_boards/targets/linsn_rv901t.py
@@ -16,6 +16,7 @@ from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 from litex.soc.cores.clock import S6PLL
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import M12L64322A
 from litedram.phy import GENSDRPHY
@@ -68,6 +69,12 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(1)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # EthernetSoC --------------------------------------------------------------------------------------
 
 class EthernetSoC(BaseSoC):
diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py
index a766557..19ad8aa 100755
--- a/litex_boards/targets/mercury_xu5.py
+++ b/litex_boards/targets/mercury_xu5.py
@@ -15,6 +15,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT40A256M16
 from litedram.phy import usddrphy
@@ -77,6 +78,12 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(3)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py
index 8441f14..3dd421d 100755
--- a/litex_boards/targets/mimas_a7.py
+++ b/litex_boards/targets/mimas_a7.py
@@ -16,6 +16,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT41J128M16
 from litedram.phy import s7ddrphy
@@ -80,6 +81,12 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py
index 500d822..39f432a 100755
--- a/litex_boards/targets/minispartan6.py
+++ b/litex_boards/targets/minispartan6.py
@@ -20,6 +20,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import AS4C16M16
 from litedram.phy import GENSDRPHY
@@ -66,6 +67,12 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py
index 90393ee..33979af 100755
--- a/litex_boards/targets/netv2.py
+++ b/litex_boards/targets/netv2.py
@@ -14,6 +14,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import K4B2G1646F
 from litedram.phy import s7ddrphy
@@ -81,6 +82,12 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(6)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py
index 881dfa9..51387d5 100755
--- a/litex_boards/targets/nexys4ddr.py
+++ b/litex_boards/targets/nexys4ddr.py
@@ -14,6 +14,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT47H64M16
 from litedram.phy import s7ddrphy
@@ -80,6 +81,12 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(16)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py
index ce01f16..1f00cb7 100755
--- a/litex_boards/targets/nexys_video.py
+++ b/litex_boards/targets/nexys_video.py
@@ -14,6 +14,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT41K256M16
 from litedram.phy import s7ddrphy
@@ -80,6 +81,12 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py
index f1919fa..d240a15 100755
--- a/litex_boards/targets/pano_logic_g2.py
+++ b/litex_boards/targets/pano_logic_g2.py
@@ -14,6 +14,7 @@ from litex_boards.platforms import pano_logic_g2
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -39,6 +40,12 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(3)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/pipistrello.py b/litex_boards/targets/pipistrello.py
index 9a989ba..d0f5407 100755
--- a/litex_boards/targets/pipistrello.py
+++ b/litex_boards/targets/pipistrello.py
@@ -20,6 +20,7 @@ from litex_boards.platforms import pipistrello
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT46H32M16
 from litedram.phy import s6ddrphy
@@ -182,6 +183,12 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(5)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py
index ef6c36f..ee6508a 100755
--- a/litex_boards/targets/tagus.py
+++ b/litex_boards/targets/tagus.py
@@ -25,6 +25,7 @@ from litex.soc.cores.clock import *
 from litex.soc.cores.dna import DNA
 from litex.soc.cores.xadc import XADC
 from litex.soc.cores.icap import ICAP
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT41J128M16
 from litedram.phy import s7ddrphy
@@ -157,6 +158,12 @@ class PCIeSoC(SoCCore):
             self.comb += self.pcie_msi.irqs[i].eq(v)
             self.add_constant(k + "_INTERRUPT", i)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(3)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
     def generate_software_headers(self):
         csr_header = get_csr_header(self.csr_regions, self.constants, with_access_functions=False)
         tools.write_to_file("csr.h", csr_header)
diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py
index 70a1cdd..243e346 100755
--- a/litex_boards/targets/trellisboard.py
+++ b/litex_boards/targets/trellisboard.py
@@ -17,6 +17,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT41J256M16
 from litedram.phy import ECP5DDRPHY
@@ -112,6 +113,12 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(12)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py
index cfa6e09..6a57848 100755
--- a/litex_boards/targets/ulx3s.py
+++ b/litex_boards/targets/ulx3s.py
@@ -21,6 +21,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram import modules as litedram_modules
 from litedram.phy import GENSDRPHY
@@ -89,6 +90,12 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py
index fb2e845..09b6ed6 100755
--- a/litex_boards/targets/vc707.py
+++ b/litex_boards/targets/vc707.py
@@ -16,6 +16,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT8JTF12864
 from litedram.phy import s7ddrphy
@@ -69,6 +70,12 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py
index d6a40d1..9baf06a 100755
--- a/litex_boards/targets/vcu118.py
+++ b/litex_boards/targets/vcu118.py
@@ -15,6 +15,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import EDY4016A
 from litedram.phy import usddrphy
@@ -77,6 +78,12 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py
index 13e13ee..bc9742d 100755
--- a/litex_boards/targets/versa_ecp5.py
+++ b/litex_boards/targets/versa_ecp5.py
@@ -18,6 +18,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT41K64M16
 from litedram.phy import ECP5DDRPHY
@@ -106,6 +107,12 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py
index 1fcc688..d77a728 100755
--- a/litex_boards/targets/zcu104.py
+++ b/litex_boards/targets/zcu104.py
@@ -15,6 +15,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MTA4ATF51264HZ
 from litedram.phy import usddrphy
@@ -76,6 +77,12 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(4)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():