From 70594a5305c720887f1c4622b35654cfaf462403 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 24 Aug 2020 09:05:27 +0200 Subject: [PATCH] ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2. --- litex_boards/platforms/ulx3s.py | 11 ++--------- litex_boards/targets/ulx3s.py | 2 +- 2 files changed, 3 insertions(+), 10 deletions(-) diff --git a/litex_boards/platforms/ulx3s.py b/litex_boards/platforms/ulx3s.py index f4b7928..7b708eb 100644 --- a/litex_boards/platforms/ulx3s.py +++ b/litex_boards/platforms/ulx3s.py @@ -45,12 +45,7 @@ _io = [ IOStandard("LVCMOS33"), ), - ("sdram_clock", 0, Pins("F19"), - Misc("PULLMODE=NONE"), - Misc("DRIVE=4"), - Misc("SLEWRATE=FAST"), - IOStandard("LVCMOS33") - ), + ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")), ("sdram", 0, Subsignal("a", Pins( "M20 M19 L20 L19 K20 K19 K18 J20", @@ -65,10 +60,8 @@ _io = [ Subsignal("cke", Pins("F20")), Subsignal("ba", Pins("P19 N20")), Subsignal("dm", Pins("U19 E20")), - Misc("PULLMODE=NONE"), - Misc("DRIVE=4"), - Misc("SLEWRATE=FAST"), IOStandard("LVCMOS33"), + Misc("SLEWRATE=FAST"), ), ("wifi_gpio0", 0, Pins("L2"), IOStandard("LVCMOS33")), diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index 1f098ea..d9baa60 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -55,7 +55,7 @@ class _CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) if sdram_rate == "1:2": pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) - pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90) + pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. else: pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)