From 70fb3de96cdf9d7e38051cd278560de08e2c566b Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 19 Jun 2024 07:59:24 +0200 Subject: [PATCH] targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU --- litex_boards/targets/digilent_arty_z7.py | 14 +++----------- litex_boards/targets/digilent_pynq_z1.py | 8 -------- litex_boards/targets/digilent_zedboard.py | 9 --------- litex_boards/targets/krtkl_snickerdoodle.py | 9 --------- litex_boards/targets/redpitaya.py | 10 ---------- litex_boards/targets/xilinx_zybo_z7.py | 10 ---------- 6 files changed, 3 insertions(+), 57 deletions(-) diff --git a/litex_boards/targets/digilent_arty_z7.py b/litex_boards/targets/digilent_arty_z7.py index 4c8ef16..04be70a 100755 --- a/litex_boards/targets/digilent_arty_z7.py +++ b/litex_boards/targets/digilent_arty_z7.py @@ -80,15 +80,15 @@ class BaseSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- use_ps7_clk = (kwargs.get("cpu_type", None) == "zynq7000") + if use_ps7_clk: + sys_clk_freq = 100e6 + self.crg = _CRG(platform, sys_clk_freq, use_ps7_clk) # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynq7000": kwargs["integrated_sram_size"] = 0 kwargs["with_uart"] = False - self.mem_map = { - 'csr': 0x4000_0000, # Zynq GP0 default - } SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty Z7", **kwargs) # Zynq7000 Integration --------------------------------------------------------------------- @@ -101,14 +101,6 @@ class BaseSoC(SoCCore): "PCW_FPGA0_PERIPHERAL_FREQMHZ" : sys_clk_freq / 1e6, }) - # Connect AXI GP0 to the SoC - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = self.mem_map["csr"]) - self.bus.add_master(master=wb_gp0) - self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], size = 512 * 1024 * 1024 - self.cpu.mem_map["sram"]) diff --git a/litex_boards/targets/digilent_pynq_z1.py b/litex_boards/targets/digilent_pynq_z1.py index a822137..3ef0db7 100755 --- a/litex_boards/targets/digilent_pynq_z1.py +++ b/litex_boards/targets/digilent_pynq_z1.py @@ -79,14 +79,6 @@ class BaseSoC(SoCCore): os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci") self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci") - # Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one) - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = 0x43c00000) - self.bus.add_master(master=wb_gp0) - # Video ------------------------------------------------------------------------------------ if with_video_terminal: self.videophy = VideoS7HDMIPHY(platform.request("hdmi_tx"), clock_domain="hdmi") diff --git a/litex_boards/targets/digilent_zedboard.py b/litex_boards/targets/digilent_zedboard.py index 206e56c..9f59d57 100755 --- a/litex_boards/targets/digilent_zedboard.py +++ b/litex_boards/targets/digilent_zedboard.py @@ -50,7 +50,6 @@ class _CRG(LiteXModule): class BaseSoC(SoCCore): - mem_map = {"csr": 0x43c0_0000} # default GP0 address on Zynq def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs): platform = digilent_zedboard.Platform() @@ -70,14 +69,6 @@ class BaseSoC(SoCCore): preset="ZedBoard", config={'PCW_FPGA0_PERIPHERAL_FREQMHZ': sys_clk_freq / 1e6}) - # Connect AXI GP0 to the SoC - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = self.mem_map["csr"]) - self.bus.add_master(master=wb_gp0) - self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], size = 512 * 1024 * 1024 - self.cpu.mem_map["sram"]) diff --git a/litex_boards/targets/krtkl_snickerdoodle.py b/litex_boards/targets/krtkl_snickerdoodle.py index c78202c..a857329 100755 --- a/litex_boards/targets/krtkl_snickerdoodle.py +++ b/litex_boards/targets/krtkl_snickerdoodle.py @@ -81,21 +81,12 @@ class BaseSoC(SoCCore): if kwargs.get("cpu_type", None) == "zynq7000": kwargs["integrated_sram_size"] = 0 kwargs["with_uart"] = False - self.mem_map = {"csr": 0x4000_0000} # Zynq GP0 default SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Snickerdoodle", **kwargs) # Zynq7000 Integration --------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynq7000": load_ps7(self, xci_file) - # Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one) - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = self.mem_map["csr"]) - self.bus.add_master(master=wb_gp0) - # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.leds = LedChaser( diff --git a/litex_boards/targets/redpitaya.py b/litex_boards/targets/redpitaya.py index e4d560f..1c34f2e 100755 --- a/litex_boards/targets/redpitaya.py +++ b/litex_boards/targets/redpitaya.py @@ -62,9 +62,6 @@ class BaseSoC(SoCCore): if kwargs.get("cpu_type", None) == "zynq7000": kwargs["integrated_sram_size"] = 0 kwargs["with_uart"] = False - self.mem_map = { - 'csr': 0x43c0_0000, # Zynq GP0 default - } SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Zebboard", **kwargs) # Zynq7000 Integration --------------------------------------------------------------------- @@ -75,13 +72,6 @@ class BaseSoC(SoCCore): os.system("cp redpitaya_ps7.txt xci/redpitaya_ps7.xci") self.cpu.set_ps7_xci("xci/redpitaya_ps7.xci") - # Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one) - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = 0x43c00000) - self.bus.add_master(master=wb_gp0) self.bus.add_region("flash", SoCRegion(origin=0xFC00_0000, size=0x4_0000, mode="rwx")) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/xilinx_zybo_z7.py b/litex_boards/targets/xilinx_zybo_z7.py index 6425780..86e344a 100755 --- a/litex_boards/targets/xilinx_zybo_z7.py +++ b/litex_boards/targets/xilinx_zybo_z7.py @@ -57,9 +57,6 @@ class BaseSoC(SoCCore): if kwargs.get("cpu_type", None) == "zynq7000": kwargs["integrated_sram_size"] = 0x0 kwargs["with_uart"] = False - self.mem_map = { - 'csr': 0x4000_0000, # Zynq GP0 default - } SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Zybo Z7/original Zybo", **kwargs) # Zynq7000 Integration --------------------------------------------------------------------- @@ -74,13 +71,6 @@ class BaseSoC(SoCCore): else: self.cpu.set_ps7(name="ps", config = platform.ps7_config) - # Connect AXI GP0 to the SoC with base address of 0x40000000 (default one) - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = 0x40000000) - self.bus.add_master(master=wb_gp0) #TODO memory size dependend on board variant self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"],