From 7442639a5e0552ed92dbe7b8ae90c034509e754b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 2 Jul 2021 09:33:06 +0200 Subject: [PATCH] targets/digilent_arty: Add default value for CRG's with_mapped_flash. Otherwise break retro-compat on external design importing CRG without passing this new parameter. --- litex_boards/targets/digilent_arty.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py index 0001b37..dd5bc2c 100755 --- a/litex_boards/targets/digilent_arty.py +++ b/litex_boards/targets/digilent_arty.py @@ -34,7 +34,7 @@ from litespi import LiteSPI # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): - def __init__(self, platform, sys_clk_freq, with_mapped_flash): + def __init__(self, platform, sys_clk_freq, with_mapped_flash=False): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)