diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py
index 185ca20..1569707 100755
--- a/litex_boards/targets/acorn_cle_215.py
+++ b/litex_boards/targets/acorn_cle_215.py
@@ -111,7 +111,6 @@ class BaseSoC(SoCCore):
             self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
                 data_width = 128,
                 bar0_size  = 0x20000)
-            self.pcie_phy.add_timing_constraints(platform)
             platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
             self.add_csr("pcie_phy")
             self.comb += platform.request("pcie_clkreq_n").eq(0)
diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py
index f2b2a17..418323d 100755
--- a/litex_boards/targets/aller.py
+++ b/litex_boards/targets/aller.py
@@ -94,7 +94,6 @@ class BaseSoC(SoCCore):
             self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
                 data_width = 128,
                 bar0_size  = 0x20000)
-            self.pcie_phy.add_timing_constraints(platform)
             platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
             self.add_csr("pcie_phy")
 
diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py
index f7317cf..0374001 100755
--- a/litex_boards/targets/alveo_u250.py
+++ b/litex_boards/targets/alveo_u250.py
@@ -100,7 +100,6 @@ class BaseSoC(SoCCore):
             self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
                 data_width = 128,
                 bar0_size  = 0x20000)
-            #self.pcie_phy.add_timing_constraints(platform) # FIXME
             platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
             self.add_csr("pcie_phy")
 
diff --git a/litex_boards/targets/fk33.py b/litex_boards/targets/fk33.py
index c0608de..310b7bb 100755
--- a/litex_boards/targets/fk33.py
+++ b/litex_boards/targets/fk33.py
@@ -58,7 +58,6 @@ class BaseSoC(SoCCore):
             self.submodules.pcie_phy = USPHBMPCIEPHY(platform, platform.request("pcie_x4"),
                 data_width = 128,
                 bar0_size  = 0x20000)
-            #self.pcie_phy.add_timing_constraints(platform) # FIXME
             platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
             self.add_csr("pcie_phy")
 
diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py
index 0643a76..54a03f9 100755
--- a/litex_boards/targets/nereid.py
+++ b/litex_boards/targets/nereid.py
@@ -91,7 +91,6 @@ class BaseSoC(SoCCore):
             self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
                 data_width = 128,
                 bar0_size  = 0x20000)
-            self.pcie_phy.add_timing_constraints(platform)
             platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
             self.add_csr("pcie_phy")
 
diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py
index 528f348..dc525aa 100755
--- a/litex_boards/targets/tagus.py
+++ b/litex_boards/targets/tagus.py
@@ -94,7 +94,6 @@ class BaseSoC(SoCCore):
             self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
                 data_width = 64,
                 bar0_size  = 0x20000)
-            self.pcie_phy.add_timing_constraints(platform)
             platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
             self.add_csr("pcie_phy")
 
diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py
index fbf3e66..a43f42a 100755
--- a/litex_boards/targets/xcu1525.py
+++ b/litex_boards/targets/xcu1525.py
@@ -98,7 +98,6 @@ class BaseSoC(SoCCore):
             self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
                 data_width = 128,
                 bar0_size  = 0x20000)
-            #self.pcie_phy.add_timing_constraints(platform) # FIXME
             platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
             self.add_csr("pcie_phy")