From 78224b1e56e42b4e332db851b24f3fd2cb0f3cb0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 21 Mar 2020 22:11:47 +0100 Subject: [PATCH] targets/colorlight_5a_75b: add SDRAM. --- litex_boards/targets/colorlight_5a_75b.py | 25 +++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/colorlight_5a_75b.py b/litex_boards/targets/colorlight_5a_75b.py index cd5c390..059e199 100755 --- a/litex_boards/targets/colorlight_5a_75b.py +++ b/litex_boards/targets/colorlight_5a_75b.py @@ -29,13 +29,17 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * +from litedram.modules import M12L16161A +from litedram.phy import GENSDRPHY + from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain() # # # @@ -48,9 +52,13 @@ class _CRG(Module): self.submodules.pll = pll = ECP5PLL() pll.register_clkin(clk25, 25e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11) + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20) self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n) + # SDRAM clock + self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): @@ -64,6 +72,19 @@ class BaseSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) + # SDR SDRAM -------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2) + self.add_sdram("sdram", + phy = self.sdrphy, + module = M12L16161A(sys_clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) + # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII(