From 785909ac5f4bd93646435ca2ccf4bf78a8c6cb15 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 9 Oct 2019 11:09:59 +0200 Subject: [PATCH] targets: switch from shadow_base to io_regions --- litex_boards/community/targets/ac701.py | 4 ++-- litex_boards/official/targets/arty.py | 4 ++-- litex_boards/official/targets/genesys2.py | 4 ++-- litex_boards/official/targets/kc705.py | 4 ++-- litex_boards/official/targets/kcu105.py | 4 ++-- litex_boards/official/targets/nexys4ddr.py | 4 ++-- litex_boards/official/targets/nexys_video.py | 4 ++-- litex_boards/official/targets/simple.py | 4 ++-- litex_boards/official/targets/versa_ecp5.py | 4 ++-- litex_boards/partner/targets/c10lprefkit.py | 4 ++-- litex_boards/partner/targets/netv2.py | 4 ++-- litex_boards/partner/targets/trellisboard.py | 4 ++-- 12 files changed, 24 insertions(+), 24 deletions(-) diff --git a/litex_boards/community/targets/ac701.py b/litex_boards/community/targets/ac701.py index e992967..7e745c4 100755 --- a/litex_boards/community/targets/ac701.py +++ b/litex_boards/community/targets/ac701.py @@ -72,7 +72,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -123,7 +123,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/arty.py b/litex_boards/official/targets/arty.py index f2ddd7b..95346b0 100755 --- a/litex_boards/official/targets/arty.py +++ b/litex_boards/official/targets/arty.py @@ -72,7 +72,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -85,7 +85,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/genesys2.py b/litex_boards/official/targets/genesys2.py index d9fa462..0c6a664 100755 --- a/litex_boards/official/targets/genesys2.py +++ b/litex_boards/official/targets/genesys2.py @@ -65,7 +65,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -78,7 +78,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/kc705.py b/litex_boards/official/targets/kc705.py index 98bd9af..f1ac9e7 100755 --- a/litex_boards/official/targets/kc705.py +++ b/litex_boards/official/targets/kc705.py @@ -67,7 +67,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -80,7 +80,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/kcu105.py b/litex_boards/official/targets/kcu105.py index 93d44ca..707423a 100755 --- a/litex_boards/official/targets/kcu105.py +++ b/litex_boards/official/targets/kcu105.py @@ -103,7 +103,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -117,7 +117,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/nexys4ddr.py b/litex_boards/official/targets/nexys4ddr.py index 994a5c8..14f35ad 100755 --- a/litex_boards/official/targets/nexys4ddr.py +++ b/litex_boards/official/targets/nexys4ddr.py @@ -71,7 +71,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/nexys_video.py b/litex_boards/official/targets/nexys_video.py index 59caa53..31294e1 100755 --- a/litex_boards/official/targets/nexys_video.py +++ b/litex_boards/official/targets/nexys_video.py @@ -70,7 +70,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -83,7 +83,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/simple.py b/litex_boards/official/targets/simple.py index a1fce67..b615a66 100755 --- a/litex_boards/official/targets/simple.py +++ b/litex_boards/official/targets/simple.py @@ -31,7 +31,7 @@ class BaseSoC(SoCCore): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -44,7 +44,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/versa_ecp5.py b/litex_boards/official/targets/versa_ecp5.py index 0bf876a..c108d32 100755 --- a/litex_boards/official/targets/versa_ecp5.py +++ b/litex_boards/official/targets/versa_ecp5.py @@ -102,7 +102,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -116,7 +116,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/partner/targets/c10lprefkit.py b/litex_boards/partner/targets/c10lprefkit.py index 3b95fa8..1bb2f51 100755 --- a/litex_boards/partner/targets/c10lprefkit.py +++ b/litex_boards/partner/targets/c10lprefkit.py @@ -110,7 +110,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -123,7 +123,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/partner/targets/netv2.py b/litex_boards/partner/targets/netv2.py index bfed8a7..1364b1d 100755 --- a/litex_boards/partner/targets/netv2.py +++ b/litex_boards/partner/targets/netv2.py @@ -71,7 +71,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/partner/targets/trellisboard.py b/litex_boards/partner/targets/trellisboard.py index f15b0d6..8654bf3 100755 --- a/litex_boards/partner/targets/trellisboard.py +++ b/litex_boards/partner/targets/trellisboard.py @@ -104,7 +104,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -118,7 +118,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac")