diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py index d0cc05f..6648a97 100755 --- a/litex_boards/targets/ac701.py +++ b/litex_boards/targets/ac701.py @@ -52,7 +52,10 @@ class BaseSoC(SoCCore): platform = ac701.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on AC701", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py index 71d2c03..b820f75 100755 --- a/litex_boards/targets/alveo_u250.py +++ b/litex_boards/targets/alveo_u250.py @@ -56,7 +56,10 @@ class BaseSoC(SoCCore): platform = alveo_u250.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Alveo U250", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py index 52b5785..2dc0338 100755 --- a/litex_boards/targets/arty.py +++ b/litex_boards/targets/arty.py @@ -56,7 +56,10 @@ class BaseSoC(SoCCore): platform = arty.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Arty A7", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/arty_s7.py b/litex_boards/targets/arty_s7.py index 1f12d2f..0e0adbc 100755 --- a/litex_boards/targets/arty_s7.py +++ b/litex_boards/targets/arty_s7.py @@ -51,7 +51,10 @@ class BaseSoC(SoCCore): platform = arty_s7.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Arty S7", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index a47fc13..7f7d1b3 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -59,7 +59,10 @@ class BaseSoC(SoCCore): platform = c10lprefkit.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on C10 LP RefKit", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index f6afa1c..ce40e50 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -74,7 +74,10 @@ class BaseSoC(SoCCore): sys_clk_freq = int(81e6) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Cam Link 4K", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py index 68b1709..26019da 100755 --- a/litex_boards/targets/colorlight_5a_75x.py +++ b/litex_boards/targets/colorlight_5a_75x.py @@ -107,7 +107,10 @@ class BaseSoC(SoCCore): sys_clk_freq = int(125e6) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Colorlight " + board.upper(), + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- with_rst = kwargs["uart_name"] not in ["serial", "bridge"] # serial_rx shared with user_btn_n. @@ -141,7 +144,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75B") + parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75X") builder_args(parser) soc_core_args(parser) trellis_args(parser) diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py index 85a884c..cbe63c4 100755 --- a/litex_boards/targets/de0nano.py +++ b/litex_boards/targets/de0nano.py @@ -50,7 +50,10 @@ class BaseSoC(SoCCore): platform = de0nano.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on DE0-Nano", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -77,7 +80,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on DE0 Nano") + parser = argparse.ArgumentParser(description="LiteX SoC on DE0-Nano") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py index 734da3e..164e8c1 100755 --- a/litex_boards/targets/de10lite.py +++ b/litex_boards/targets/de10lite.py @@ -55,7 +55,10 @@ class BaseSoC(SoCCore): platform = de10lite.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on DE10-Lite", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -95,7 +98,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Lite") + parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Lite") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py index ad34c53..44a43c1 100755 --- a/litex_boards/targets/de10nano.py +++ b/litex_boards/targets/de10nano.py @@ -55,7 +55,10 @@ class BaseSoC(SoCCore): platform = de10nano.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on DE10-Nano", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=with_mister_sdram) @@ -95,7 +98,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Nano") + parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Nano") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) diff --git a/litex_boards/targets/de1soc.py b/litex_boards/targets/de1soc.py index 1707620..1dc0faf 100755 --- a/litex_boards/targets/de1soc.py +++ b/litex_boards/targets/de1soc.py @@ -49,7 +49,10 @@ class BaseSoC(SoCCore): platform = de1soc.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on DE1-SoC", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/de2_115.py b/litex_boards/targets/de2_115.py index a8aab1a..4a2e0a2 100755 --- a/litex_boards/targets/de2_115.py +++ b/litex_boards/targets/de2_115.py @@ -49,7 +49,10 @@ class BaseSoC(SoCCore): platform = de2_115.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on DE2-115", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/ecp5_evn.py b/litex_boards/targets/ecp5_evn.py index 8b81ad7..11208e1 100755 --- a/litex_boards/targets/ecp5_evn.py +++ b/litex_boards/targets/ecp5_evn.py @@ -46,7 +46,10 @@ class BaseSoC(SoCCore): platform = ecp5_evn.Platform(toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on ECP5 Evaluation Board", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- crg = _CRG(platform, sys_clk_freq, x5_clk_freq) diff --git a/litex_boards/targets/ecpix5.py b/litex_boards/targets/ecpix5.py index dd60861..6149c6e 100755 --- a/litex_boards/targets/ecpix5.py +++ b/litex_boards/targets/ecpix5.py @@ -77,7 +77,10 @@ class BaseSoC(SoCCore): platform = ecpix5.Platform(toolchain="trellis") # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on ECPIX-5", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/forest_kitten_33.py b/litex_boards/targets/forest_kitten_33.py index 11ddc9e..2ee18f9 100755 --- a/litex_boards/targets/forest_kitten_33.py +++ b/litex_boards/targets/forest_kitten_33.py @@ -34,7 +34,10 @@ class BaseSoC(SoCCore): platform = forest_kitten_33.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Forest Kitten 33", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py index 80f9169..72e42c9 100755 --- a/litex_boards/targets/genesys2.py +++ b/litex_boards/targets/genesys2.py @@ -47,7 +47,10 @@ class BaseSoC(SoCCore): platform = genesys2.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Genesys2", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py index 2e5cd30..a7124c9 100755 --- a/litex_boards/targets/hadbadge.py +++ b/litex_boards/targets/hadbadge.py @@ -57,7 +57,10 @@ class BaseSoC(SoCCore): platform = hadbadge.Platform(toolchain=toolchain) # SoCCore --------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Hackaday Badge", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/icebreaker.py b/litex_boards/targets/icebreaker.py index def67e0..f6ccc8b 100755 --- a/litex_boards/targets/icebreaker.py +++ b/litex_boards/targets/icebreaker.py @@ -80,7 +80,10 @@ class BaseSoC(SoCCore): kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on iCEBreaker", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index e6511c1..1c7a04c 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -49,7 +49,10 @@ class BaseSoC(SoCCore): platform = kc705.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on KC705", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index fc3829c..397e949 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -56,7 +56,10 @@ class BaseSoC(SoCCore): platform = kcu105.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on KCU105", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/kx2.py b/litex_boards/targets/kx2.py index 5f25baa..480a58f 100755 --- a/litex_boards/targets/kx2.py +++ b/litex_boards/targets/kx2.py @@ -46,7 +46,10 @@ class BaseSoC(SoCCore): platform = kx2.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on KX2", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index d6acfb1..95db820 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -51,7 +51,10 @@ class BaseSoC(SoCCore): sys_clk_freq = int(75e6) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Linsn RV901T", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index 911c91e..efc2f30 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -104,7 +104,10 @@ class BaseSoC(SoCCore): sys.path.append("valentyusb") # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Logicbone", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py index b7dd620..739e8df 100755 --- a/litex_boards/targets/mercury_xu5.py +++ b/litex_boards/targets/mercury_xu5.py @@ -55,7 +55,10 @@ class BaseSoC(SoCCore): platform = mercury_xu5.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Mercury XU5", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -87,7 +90,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on Enclustra's Mercury XU5") + parser = argparse.ArgumentParser(description="LiteX SoC on Mercury XU5") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py index c3f3d0f..0be9c60 100755 --- a/litex_boards/targets/mimas_a7.py +++ b/litex_boards/targets/mimas_a7.py @@ -51,7 +51,10 @@ class BaseSoC(SoCCore): platform = mimas_a7.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Mimas A7", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py index 5b9862c..44c9977 100755 --- a/litex_boards/targets/minispartan6.py +++ b/litex_boards/targets/minispartan6.py @@ -49,7 +49,10 @@ class BaseSoC(SoCCore): platform = minispartan6.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on MiniSpartan6", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py index 39b04df..7ebc081 100755 --- a/litex_boards/targets/netv2.py +++ b/litex_boards/targets/netv2.py @@ -52,7 +52,10 @@ class BaseSoC(SoCCore): platform = netv2.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on NeTV2", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py index 835ebf5..32e8fde 100755 --- a/litex_boards/targets/nexys4ddr.py +++ b/litex_boards/targets/nexys4ddr.py @@ -53,7 +53,10 @@ class BaseSoC(SoCCore): platform = nexys4ddr.Platform() # SoCCore ----------------------------------_----------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Nexys4DDR", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py index ff283bd..b267e3c 100755 --- a/litex_boards/targets/nexys_video.py +++ b/litex_boards/targets/nexys_video.py @@ -53,7 +53,10 @@ class BaseSoC(SoCCore): platform = nexys_video.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Nexys Video", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index d0099f6..73c7290 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -34,7 +34,6 @@ class _CRG(Module): self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True) - # # # self.stop = Signal() @@ -102,7 +101,10 @@ class BaseSoC(SoCCore): platform.add_extension(orangecrab.feather_serial) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on OrangeCrab", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py index 95a18d8..da6b219 100755 --- a/litex_boards/targets/pano_logic_g2.py +++ b/litex_boards/targets/pano_logic_g2.py @@ -45,7 +45,10 @@ class BaseSoC(SoCCore): sys_clk_freq = int(125e6) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Pano Logic G2", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_ethernet or with_etherbone) diff --git a/litex_boards/targets/pipistrello.py b/litex_boards/targets/pipistrello.py index aac4179..a0c5048 100755 --- a/litex_boards/targets/pipistrello.py +++ b/litex_boards/targets/pipistrello.py @@ -154,8 +154,11 @@ class BaseSoC(SoCCore): sys_clk_freq = (83 + Fraction(1, 3))*1000*1000 platform = pipistrello.Platform() - # SoCCore -----------------------------------------------------------------_---------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Pipistrello", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/simple.py b/litex_boards/targets/simple.py index 0954a1e..3cfe495 100755 --- a/litex_boards/targets/simple.py +++ b/litex_boards/targets/simple.py @@ -24,7 +24,10 @@ class BaseSoC(SoCCore): sys_clk_freq = int(1e9/platform.default_clk_period) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX Simple SoC", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request(platform.default_clk_name)) diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index d14336b..a0c4938 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -88,8 +88,11 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", with_ethernet=False, **kwargs): platform = trellisboard.Platform(toolchain=toolchain) - # SoCCore -----------------------------------------------------------------_---------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Trellis Board", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index 9bad61d..3a4b322 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -74,7 +74,10 @@ class BaseSoC(SoCCore): platform = ulx3s.Platform(device=device, toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on ULX3S", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py index 7f236d5..feaef4f 100755 --- a/litex_boards/targets/vc707.py +++ b/litex_boards/targets/vc707.py @@ -46,8 +46,11 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = vc707.Platform() - # SoCCore ------------------------------------------------------------------_--------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on VC707", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py index 317de82..de04883 100755 --- a/litex_boards/targets/vcu118.py +++ b/litex_boards/targets/vcu118.py @@ -55,7 +55,10 @@ class BaseSoC(SoCCore): platform = vcu118.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on VCU118", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 7bbd7ad..8eb5ca2 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -83,7 +83,10 @@ class BaseSoC(SoCCore): kwargs["integrated_rom_size"] = 0xb000 if with_ethernet else 0x9000 # SoCCore -----------------------------------------_---------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Versa ECP5", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py index 3788f99..fd04333 100755 --- a/litex_boards/targets/zcu104.py +++ b/litex_boards/targets/zcu104.py @@ -55,7 +55,10 @@ class BaseSoC(SoCCore): platform = zcu104.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on ZCU104", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq)