From 7a738245af94e4ad4cfed77c00c127d72ded769f Mon Sep 17 00:00:00 2001 From: Sergiu Mosanu Date: Thu, 14 Jan 2021 21:53:25 -0500 Subject: [PATCH] fix bitstream problem --- litex_boards/platforms/alveo_u280.py | 73 ++-------------------------- litex_boards/targets/alveo_u280.py | 13 +---- 2 files changed, 7 insertions(+), 79 deletions(-) diff --git a/litex_boards/platforms/alveo_u280.py b/litex_boards/platforms/alveo_u280.py index 25dc6de..776d666 100644 --- a/litex_boards/platforms/alveo_u280.py +++ b/litex_boards/platforms/alveo_u280.py @@ -23,64 +23,22 @@ _io = [ ), ("cpu_reset", 0, Pins("L30"), IOStandard("LVCMOS18")), - # Leds - ("user_led", 0, Pins("C32"), IOStandard("LVCMOS18")), - ("user_led", 1, Pins("D32"), IOStandard("LVCMOS18")), - ("user_led", 2, Pins("D31"), IOStandard("LVCMOS18")), - # Serial ("serial", 0, Subsignal("rx", Pins("A28"), IOStandard("LVCMOS18")), Subsignal("tx", Pins("B33"), IOStandard("LVCMOS18")), ), - # # PCIe - # ("pcie_x2", 0, - # Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), - # Subsignal("clk_n", Pins("AM10")), - # Subsignal("clk_p", Pins("AM11")), - # Subsignal("rx_n", Pins("AF1 AG3")), - # Subsignal("rx_p", Pins("AF2 AG4")), - # Subsignal("tx_n", Pins("AF6 AG8")), - # Subsignal("tx_p", Pins("AF7 AG9")), - # ), - # ("pcie_x4", 0, - # Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), - # Subsignal("clk_n", Pins("AM10")), - # Subsignal("clk_p", Pins("AM11")), - # Subsignal("rx_n", Pins("AF1 AG3 AH1 AJ3")), - # Subsignal("rx_p", Pins("AF2 AG4 AH2 AJ4")), - # Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8")), - # Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9")), - # ), - # ("pcie_x8", 0, - # Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), - # Subsignal("clk_n", Pins("AM10")), - # Subsignal("clk_p", Pins("AM11")), - # Subsignal("rx_n", Pins("AF1 AG3 AH1 AJ3 AK1 AL3 AM1 AN3")), - # Subsignal("rx_p", Pins("AF2 AG4 AH2 AJ4 AK2 AL4 AM2 AN4")), - # Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8 AK6 AL8 AM6 AN8")), - # Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9 AK7 AL9 AM7 AN9")), - # ), - # ("pcie_x16", 0, - # Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), - # Subsignal("clk_n", Pins("AM10")), - # Subsignal("clk_p", Pins("AM11")), - # Subsignal("rx_n", Pins("AF1 AG3 AH1 AJ3 AK1 AL3 AM1 AN3 AP1 AR3 AT1 AU3 AV1 AW3 BA1 BC1")), - # Subsignal("rx_p", Pins("AF2 AG4 AH2 AJ4 AK2 AL4 AM2 AN4 AP2 AR4 AT2 AU4 AV2 AW4 BA2 BC2")), - # Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8 AK6 AL8 AM6 AN8 AP6 AR8 AT6 AU8 AV6 BB4 BD4 BF4")), - # Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9 AK7 AL9 AM7 AN9 AP7 AR9 AT7 AU9 AV7 BB5 BD5 BF5")), - # ), - # DDR4 SDRAM + #("ddram_reset_gate", 0, Pins("AU21"), IOStandard("LVCMOS12")), ("ddram", 0, Subsignal("a", Pins( "BF46 BG43 BK45 BF42 BL45 BF43 BG42 BL43", "BK43 BM42 BG45 BD41 BL42 BE44"), #"BE43 BL46 BH44" IOStandard("SSTL12_DCI")), Subsignal("act_n", Pins("BH41"), IOStandard("SSTL12_DCI")), - Subsignal("ba", Pins("BH45 BM47"), IOStandard("SSTL12_DCI")), - Subsignal("bg", Pins("BF41 BE41"), IOStandard("SSTL12_DCI")), + Subsignal("ba", Pins("BH45 BM47"), IOStandard("SSTL12_DCI")), + Subsignal("bg", Pins("BF41 BE41"), IOStandard("SSTL12_DCI")), Subsignal("ras_n", Pins("BH44"), IOStandard("SSTL12_DCI")), # A16 Subsignal("cas_n", Pins("BL46"), IOStandard("SSTL12_DCI")), # A15 Subsignal("we_n", Pins("BE43"), IOStandard("SSTL12_DCI")), # A14 @@ -115,7 +73,7 @@ _io = [ # Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), - Subsignal("odt", Pins("BG44"), IOStandard("SSTL12_DCI")), + Subsignal("odt", Pins("BG44"), IOStandard("SSTL12_DCI")), Subsignal("reset_n", Pins("BG33"), IOStandard("LVCMOS12")), Misc("SLEW=FAST") ), @@ -155,25 +113,4 @@ class Platform(XilinxPlatform): self.add_platform_command("set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]") self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]") self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]") - self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]") - # ------------------------------------------------------------------------ - # # DDR4 memory channel C0 Clock constraint / Internal Vref - # self.add_period_constraint(self.lookup_request("clk300", 0, loose=True), 1e9/300e6) - # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 40]") - # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 41]") - # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 42]") - # # DDR4 memory channel C1 Clock constraint / Internal Vref - # self.add_period_constraint(self.lookup_request("clk300", 1, loose=True), 1e9/300e6) - # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]") - # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]") - # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 67]") - # # DDR4 memory channel C2 Clock constraint / Internal Vref - # self.add_period_constraint(self.lookup_request("clk300", 2, loose=True), 1e9/300e6) - # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 46]") - # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 47]") - # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 48]") - # # DDR4 memory channel C3 Clock constraint / Internal Vref - # self.add_period_constraint(self.lookup_request("clk300", 3, loose=True), 1e9/300e6) - # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 70]") - # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 71]") - # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 72]") + self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]") \ No newline at end of file diff --git a/litex_boards/targets/alveo_u280.py b/litex_boards/targets/alveo_u280.py index 13c15ac..9821c3b 100755 --- a/litex_boards/targets/alveo_u280.py +++ b/litex_boards/targets/alveo_u280.py @@ -19,7 +19,6 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * -from litex.soc.cores.led import LedChaser from litedram.modules import MTA18ASF2G72PZ from litedram.phy import usddrphy @@ -66,7 +65,7 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, - ident = "LiteX SoC on AlveoU280", + ident = "LiteX SoC on Alveo U280", ident_version = True, **kwargs) @@ -91,8 +90,6 @@ class BaseSoC(SoCCore): l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) - # Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. - platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------ self.add_ram("firmware_ram", 0x20000000, 0x8000) @@ -105,16 +102,10 @@ class BaseSoC(SoCCore): self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) - # Leds ------------------------------------------------------------------------------------- - self.submodules.leds = LedChaser( - pads = platform.request_all("user_led"), - sys_clk_freq = sys_clk_freq) - self.add_csr("leds") - # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on AlveoU280") + parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U280") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)")