From 7a9f1754501e1fe92ac03135d1854e51ba0de088 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 12 Nov 2020 12:08:20 +0100
Subject: [PATCH] targets/pcie: remove force of csr_data_width to 32 (this is
now the default) but just add a check on the pcie block.
---
litex_boards/targets/acorn_cle_215.py | 6 ++----
litex_boards/targets/aller.py | 4 +---
litex_boards/targets/alveo_u250.py | 4 +---
litex_boards/targets/fk33.py | 4 +---
litex_boards/targets/nereid.py | 4 +---
litex_boards/targets/tagus.py | 4 +---
litex_boards/targets/xcu1525.py | 6 ++----
7 files changed, 9 insertions(+), 23 deletions(-)
diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py
index bbde93e..c262aaa 100755
--- a/litex_boards/targets/acorn_cle_215.py
+++ b/litex_boards/targets/acorn_cle_215.py
@@ -108,6 +108,7 @@ class BaseSoC(SoCCore):
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
+ assert self.csr_data_width == 32
# PHY
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
@@ -172,10 +173,7 @@ def main():
soc_sdram_args(parser)
args = parser.parse_args()
- # Enforce arguments
- args.csr_data_width = 32
-
- soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args))
+ soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py
index cc18085..aec5a6d 100755
--- a/litex_boards/targets/aller.py
+++ b/litex_boards/targets/aller.py
@@ -91,6 +91,7 @@ class BaseSoC(SoCCore):
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
+ assert self.csr_data_width == 32
# PHY
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
@@ -144,9 +145,6 @@ def main():
soc_sdram_args(parser)
args = parser.parse_args()
- # Enforce arguments
- args.csr_data_width = 32
-
platform = aller.Platform()
soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py
index 677946d..65c7623 100755
--- a/litex_boards/targets/alveo_u250.py
+++ b/litex_boards/targets/alveo_u250.py
@@ -97,6 +97,7 @@ class BaseSoC(SoCCore):
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
+ assert self.csr_data_width == 32
# PHY
self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
@@ -150,9 +151,6 @@ def main():
soc_sdram_args(parser)
args = parser.parse_args()
- # Enforce arguments
- args.csr_data_width = 32
-
soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
diff --git a/litex_boards/targets/fk33.py b/litex_boards/targets/fk33.py
index d042e42..c002c8d 100755
--- a/litex_boards/targets/fk33.py
+++ b/litex_boards/targets/fk33.py
@@ -56,6 +56,7 @@ class BaseSoC(SoCCore):
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
+ assert self.csr_data_width == 32
# PHY
self.submodules.pcie_phy = USPHBMPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
@@ -109,9 +110,6 @@ def main():
soc_core_args(parser)
args = parser.parse_args()
- # Enforce arguments
- args.csr_data_width = 32
-
soc = BaseSoC(with_pcie=args.with_pcie, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py
index 30dc47a..a2f562f 100755
--- a/litex_boards/targets/nereid.py
+++ b/litex_boards/targets/nereid.py
@@ -88,6 +88,7 @@ class BaseSoC(SoCCore):
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
+ assert self.csr_data_width == 32
# PHY
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
@@ -135,9 +136,6 @@ def main():
soc_sdram_args(parser)
args = parser.parse_args()
- # Enforce arguments
- args.csr_data_width = 32
-
platform = nereid.Platform()
soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py
index e716a85..97e4d28 100755
--- a/litex_boards/targets/tagus.py
+++ b/litex_boards/targets/tagus.py
@@ -91,6 +91,7 @@ class BaseSoC(SoCCore):
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
+ assert self.csr_data_width == 32
# PHY
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
data_width = 64,
@@ -144,9 +145,6 @@ def main():
soc_sdram_args(parser)
args = parser.parse_args()
- # Enforce arguments
- args.csr_data_width = 32
-
platform = tagus.Platform()
soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py
index 3263b69..f246b30 100755
--- a/litex_boards/targets/xcu1525.py
+++ b/litex_boards/targets/xcu1525.py
@@ -95,6 +95,7 @@ class BaseSoC(SoCCore):
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
+ assert self.csr_data_width == 32
# PHY
self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
@@ -149,10 +150,7 @@ def main():
soc_sdram_args(parser)
args = parser.parse_args()
- # Enforce arguments
- args.csr_data_width = 32
-
- soc = BaseSoC(
+ soc = BaseSoC(
ddram_channel = int(args.ddram_channel, 0),
with_pcie = args.with_pcie,
**soc_sdram_argdict(args))