diff --git a/litex_boards/official/platforms/minispartan6.py b/litex_boards/official/platforms/minispartan6.py
index f8538ca..e390c91 100644
--- a/litex_boards/official/platforms/minispartan6.py
+++ b/litex_boards/official/platforms/minispartan6.py
@@ -73,14 +73,11 @@ _io = [
         IOStandard("LVCMOS33"), Drive(8), Misc("SLEW=FAST")
     ),
 
-    ("sd", 0,
-        Subsignal("sck", Pins("L12")),
-        Subsignal("d3", Pins("K12")),
-        Subsignal("d", Pins("M10")),
-        Subsignal("d1", Pins("L10")),
-        Subsignal("d2", Pins("J11")),
-        Subsignal("cmd", Pins("K11")),
-        IOStandard("LVCMOS33")
+    ("sdcard", 0,
+        Subsignal("data", Pins("M10 L10 J11 K12"), Misc("PULLUP")),
+        Subsignal("cmd", Pins("K11"), Misc("PULLUP")),
+        Subsignal("clk", Pins("L12")),
+        IOStandard("LVCMOS33"), Misc("SLEW=FAST")
     ),
 
     ("dvi_in", 0,
@@ -118,6 +115,7 @@ class Platform(XilinxPlatform):
     default_clk_period = 1e9/32e6
 
     def __init__(self, device="xc6slx25"):
+        assert device in ["xc6slx9", "xc6slx25"]
         XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
 
     def create_programmer(self):
diff --git a/litex_boards/official/targets/nexys4ddr.py b/litex_boards/official/targets/nexys4ddr.py
index fdb48c4..fa5c164 100755
--- a/litex_boards/official/targets/nexys4ddr.py
+++ b/litex_boards/official/targets/nexys4ddr.py
@@ -68,7 +68,6 @@ class BaseSoC(SoCSDRAM):
             self.register_sdram(self.ddrphy,
                 geom_settings   = sdram_module.geom_settings,
                 timing_settings = sdram_module.timing_settings)
-            self.add_constant("MEMTEST_ADDR_SIZE", 0) # FIXME
 
 # EthernetSoC --------------------------------------------------------------------------------------