From 7b6b71d4e34dc8fb0da397b321ea94569c7a4285 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 3 Sep 2020 19:48:23 +0200 Subject: [PATCH] xcu1525: add initial DDR4 support in C0 (untested). --- litex_boards/platforms/xcu1525.py | 46 +++++++++++++++++++++++++++++++ litex_boards/targets/xcu1525.py | 38 ++++++++++++++++++++++++- 2 files changed, 83 insertions(+), 1 deletion(-) diff --git a/litex_boards/platforms/xcu1525.py b/litex_boards/platforms/xcu1525.py index 4e16f4c..98d55d7 100644 --- a/litex_boards/platforms/xcu1525.py +++ b/litex_boards/platforms/xcu1525.py @@ -35,6 +35,49 @@ _io = [ Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8")), Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9")), ), + + # ddram + ("ddram", 0, + Subsignal("a", Pins( + "AT36 AV36 AV37 AW35 AW36 AY36 AY35 BA40", + "BA37 BB37 AR35 BA39 BB40 AN36"), + IOStandard("SSTL12_DCI")), + Subsignal("act_n", Pins("BB39"), IOStandard("SSTL12_DCI")), + Subsignal("ba", Pins("AT35 AT34"), IOStandard("SSTL12_DCI")), + Subsignal("bg", Pins("BC37 BC39"), IOStandard("SSTL12_DCI")), + Subsignal("cas_n", Pins("AP36"), IOStandard("SSTL12_DCI")), + Subsignal("cke", Pins("BC38"), IOStandard("SSTL12_DCI")), + Subsignal("clk_n", Pins("AW38"), IOStandard("DIFF_SSTL12_DCI")), + Subsignal("clk_p", Pins("AV38"), IOStandard("DIFF_SSTL12_DCI")), + Subsignal("cs_n", Pins("AR33"), IOStandard("SSTL12_DCI")), + Subsignal("dm", Pins("AM32 AP31 AL29 AT30 AU30 AY28 BE36 BE32"), + IOStandard("POD12_DCI")), + Subsignal("dq", Pins( + "AW28 AW29 BA28 BA27 BB29 BA29 BC27 BB27", + "BE28 BF28 BE30 BD30 BF27 BE27 BF30 BF29", + "BB31 BB32 AY32 AY33 BC32 BC33 BB34 BC34", + "AV31 AV32 AV34 AW34 AW31 AY31 BA35 BA34", + "AL30 AM30 AU32 AT32 AN31 AN32 AR32 AR31", + "AP29 AP28 AN27 AM27 AN29 AM29 AR27 AR28", + "AT28 AV27 AU27 AT27 AV29 AY30 AW30 AV28", + "BD34 BD33 BE33 BD35 BF32 BF33 BF34 BF35"), + IOStandard("POD12_DCI"), + Misc("PRE_EMPHASIS=RDRV_240"), + Misc("EQUALIZATION=EQ_LEVEL2")), + Subsignal("dqs_n", Pins("BB30 BC26 BD29 BE26 BB36 BD31 AW33 BA33"), + IOStandard("DIFF_POD12"), + Misc("PRE_EMPHASIS=RDRV_240"), + Misc("EQUALIZATION=EQ_LEVEL2")), + Subsignal("dqs_p", Pins("BA30 BB26 BD28 BD26 BB35 BC31 AV33 BA32"), + IOStandard("DIFF_POD12"), + Misc("PRE_EMPHASIS=RDRV_240"), + Misc("EQUALIZATION=EQ_LEVEL2")), + Subsignal("odt", Pins("AP34"), IOStandard("SSTL12_DCI")), + Subsignal("ras_n", Pins("AR36"), IOStandard("SSTL12_DCI")), + Subsignal("reset_n", Pins("AU31"), IOStandard("LVCMOS12")), + Subsignal("we_n", Pins("AP35"), IOStandard("SSTL12_DCI")), + Misc("SLEW=FAST") + ), ] _connectors = [] @@ -58,3 +101,6 @@ class Platform(XilinxPlatform): self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]") # Reduce programming time self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]") + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 61]") + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 62]") + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 63]") diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py index 8865d48..4da3f5a 100755 --- a/litex_boards/targets/xcu1525.py +++ b/litex_boards/targets/xcu1525.py @@ -16,6 +16,9 @@ from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser +from litedram.modules import MT40A512M8 +from litedram.phy import usddrphy + from litepcie.phy.usppciephy import USPPCIEPHY from litepcie.core import LitePCIeEndpoint, LitePCIeMSI from litepcie.frontend.dma import LitePCIeDMA @@ -27,12 +30,27 @@ from litepcie.software import generate_litepcie_software class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) + self.clock_domains.cd_clk500 = ClockDomain() # # # self.submodules.pll = pll = USPMMCM(speedgrade=-2) pll.register_clkin(platform.request("clk300"), 300e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) + pll.create_clkout(self.cd_clk500, 500e6, with_reset=False) + + self.specials += [ + Instance("BUFGCE_DIV", name="main_bufgce_div", + p_BUFGCE_DIVIDE=4, + i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), + Instance("BUFGCE", name="main_bufgce", + i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), + AsyncResetSynchronizer(self.cd_clk500, ~pll.locked), + ] + + self.submodules.idelayctrl = USPIDELAYCTRL(cd_ref=self.cd_clk500, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------ @@ -49,6 +67,24 @@ class BaseSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) + # DDR4 SDRAM ------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), + memtype = "DDR4", + sys_clk_freq = sys_clk_freq, + iodelay_clk_freq = 500e6, + cmd_latency = 1) + self.add_csr("ddrphy") + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT40A512M8(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) + # PCIe ------------------------------------------------------------------------------------- if with_pcie: # PHY