diff --git a/litex_boards/platforms/antmicro_sdi_mipi_video_converter.py b/litex_boards/platforms/antmicro_sdi_mipi_video_converter.py index 05c3f06..a5ecdd3 100644 --- a/litex_boards/platforms/antmicro_sdi_mipi_video_converter.py +++ b/litex_boards/platforms/antmicro_sdi_mipi_video_converter.py @@ -5,30 +5,32 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.lattice import LatticePlatform +from litex.build.lattice import LatticeNexusPlatform from litex.build.lattice.programmer import LatticeProgrammer from litex.build.lattice.programmer import EcpprogProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk. ("clk12", 0, Pins("G15"), IOStandard("LVCMOS33")), + # Serial. ("serial", 0, Subsignal("tx", Pins("J12"), IOStandard("LVCMOS33")), Subsignal("rx", Pins("J11"), IOStandard("LVCMOS33")), ), - # Section 7.3 General Purpose LEDs + # Leds (Section 7.3). ("user_led", 0, Pins("E15"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("E16"), IOStandard("LVCMOS33")), - # Section 7.1 DIP Switch + # DIP Switches (Section 7.1). ("user_dip_btn", 0, Pins("F15"), IOStandard("LVCMOS33")), ("user_dip_btn", 1, Pins("H10"), IOStandard("LVCMOS33")), - # Section 6.3.1. SPI Configuration + # SPI Flash (Section 6.3.1.). ("spiflash", 0, Subsignal("cs_n", Pins("C15")), Subsignal("clk", Pins("C16")), @@ -38,17 +40,13 @@ _io = [ ) ] - # Connectors --------------------------------------------------------------------------------------- _connectors = [] -# Test and Demo ------------------------------------------------------------------------------------ - - # Platform ----------------------------------------------------------------------------------------- -class Platform(LatticePlatform): +class Platform(LatticeNexusPlatform): default_clk_name = "clk12" default_clk_period = 1e9/12e6 @@ -59,7 +57,7 @@ class Platform(LatticePlatform): if device == "LIFCL": device == "LIFCL-40-9BG400C" assert device in ["LIFCL-40-9BG256C", "LIFCL-40-9BG400C", "LIFCL-40-8BG400CES", "LIFCL-40-8BG400CES2", "LIFCL-40-8BG400C"] - LatticePlatform.__init__(self, device, _io, _connectors, toolchain=toolchain, **kwargs) + LatticeNexusPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain, **kwargs) def create_programmer(self, mode="direct", prog="radiant"): assert mode in ["direct", "flash"] diff --git a/litex_boards/targets/antmicro_sdi_mipi_video_converter.py b/litex_boards/targets/antmicro_sdi_mipi_video_converter.py index f2d9b7e..1d783ba 100755 --- a/litex_boards/targets/antmicro_sdi_mipi_video_converter.py +++ b/litex_boards/targets/antmicro_sdi_mipi_video_converter.py @@ -11,7 +11,9 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -import litex_boards.platforms.antmicro_sdi_mipi_video_converter +from litex.gen import LiteXModule + +from litex_boards.platforms import antmicro_sdi_mipi_video_converter from litex.soc.cores.ram import NXLRAM from litex.soc.cores.clock import NXPLL @@ -23,33 +25,29 @@ from litex.soc.integration.soc import SoCRegion from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser -from litex.build.lattice.oxide import oxide_args, oxide_argdict -from litex.build.lattice.radiant import radiant_build_argdict, radiant_build_args - kB = 1024 mB = 1024*kB - # CRG ---------------------------------------------------------------------------------------------- -class _CRG(Module): +class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_por = ClockDomain() - self.clock_domains.cd_sys = ClockDomain() + self.cd_por = ClockDomain() + self.cd_sys = ClockDomain() # Built in OSC - self.submodules.hf_clk = NXOSCA() + self.hf_clk = NXOSCA() hf_clk_freq = 25e6 self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq) # Power on reset por_count = Signal(16, reset=2**16-1) - por_done = Signal() + por_done = Signal() self.comb += por_done.eq(por_count == 0) self.sync.por += If(~por_done, por_count.eq(por_count - 1)) # PLL - self.submodules.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True) + self.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True) sys_pll.register_clkin(self.cd_por.clk, hf_clk_freq) sys_pll.create_clkout(self.cd_sys, sys_clk_freq) self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked | ~por_done) @@ -59,72 +57,60 @@ class _CRG(Module): class BaseSoC(SoCCore): mem_map = { - "rom": 0x00000000, - "sram": 0x40000000, - "main_ram": 0x60000000, - "csr": 0xf0000000, + "rom" : 0x00000000, + "sram" : 0x40000000, + "main_ram" : 0x60000000, + "csr" : 0xf0000000, } - def __init__(self, sys_clk_freq=int(75e6), device="LIFCL-40-9BG256C", toolchain="radiant", with_led_chaser=True, **kwargs): - platform = litex_boards.platforms.antmicro_sdi_mipi_video_converter.Platform( - device=device, toolchain=toolchain) + def __init__(self, sys_clk_freq=int(75e6), device="LIFCL-40-9BG256C", toolchain="radiant", + with_led_chaser = True, + **kwargs): + platform = antmicro_sdi_mipi_video_converter.Platform(device=device, toolchain=toolchain) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq) + self.crg = _CRG(platform, sys_clk_freq) # SoCCore -----------------------------------------_---------------------------------------- # Disable Integrated SRAM since we want to instantiate LRAM specifically for it kwargs["integrated_sram_size"] = 0 - SoCCore.__init__(self, platform, sys_clk_freq, - ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Antmicro SDI MIPI Video Converter Board", **kwargs) # 128KB LRAM (used as SRAM) --------------------------------------------------------------- - - self.submodules.spram = NXLRAM(32, 64*kB) + self.spram = NXLRAM(32, 64*kB) self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=16*kB)) - self.submodules.main_ram = NXLRAM(32, 64*kB) + self.main_ram = NXLRAM(32, 64*kB) self.bus.add_slave("main_ram", self.main_ram.bus, SoCRegion(origin=self.mem_map["main_ram"], size=64*kB)) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: - self.submodules.leds = LedChaser( - pads=Cat(*[platform.request("user_led", i) for i in range(2)]), - sys_clk_freq=sys_clk_freq) + self.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) # Build -------------------------------------------------------------------------------------------- def main(): - from litex.soc.integration.soc import LiteXSoCArgumentParser - parser = LiteXSoCArgumentParser(description="LiteX SoC on Crosslink-NX Eval Board") - target_group = parser.add_argument_group(title="Target options") - target_group.add_argument("--build", action="store_true", help="Build design.") - target_group.add_argument("--load", action="store_true", help="Load bitstream.") - target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).") - target_group.add_argument("--device", default="LIFCL-40-9BG256C", help="FPGA device (LIFCL-40-9BG400C, LIFCL-40-8BG400CES, or LIFCL-40-8BG400CES2).") - target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") - target_group.add_argument("--programmer", default="radiant", help="Programmer (radiant or ecpprog).") - target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).") - - builder_args(parser) - soc_core_args(parser) - oxide_args(parser) - radiant_build_args(parser) + from litex.build.parser import LiteXArgumentParser + parser = LiteXArgumentParser(platform=antmicro_sdi_mipi_video_converter.Platform, description="LiteX SoC on Antmicro SDI MIPI Video Converter Board.") + parser.add_target_argument("--device", default="LIFCL-40-9BG256C", help="FPGA device (LIFCL-40-9BG400C, LIFCL-40-8BG400CES, or LIFCL-40-8BG400CES2).") + parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") + parser.add_target_argument("--programmer", default="radiant", help="Programmer (radiant or ecpprog).") + parser.add_target_argument("--prog-target", default="direct", help="Programming Target (direct or flash).") args = parser.parse_args() soc = BaseSoC( - sys_clk_freq=int(float(args.sys_clk_freq)), - device=args.device, - toolchain=args.toolchain, - **soc_core_argdict(args) + sys_clk_freq = int(float(args.sys_clk_freq)), + device = args.device, + toolchain = args.toolchain, + **parser.soc_argdict ) - - builder = Builder(soc, **builder_argdict(args)) - builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else radiant_build_argdict(args) + builder = Builder(soc, **parser.builder_argdict) if args.build: - builder.build(**builder_kargs) + builder.build(**parser.toolchain_argdict) if args.load: prog = soc.platform.create_programmer(args.prog_target, args.programmer)