From 7c48af9b50ed7fc595717b30b62d3da5e5388efd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 1 Feb 2021 13:22:57 +0100 Subject: [PATCH] tec0117: get SDRAM working and increase sys_clk_freq to 25MHz. ./tec0117.py --build --load Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX: __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Feb 1 2021 13:09:35 BIOS CRC passed (5abceb2e) Migen git sha1: 40b1092 LiteX git sha1: f324f953 --=============== SoC ==================-- CPU: VexRiscv_Lite @ 25MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 24KiB SRAM: 4KiB L2: 0KiB SDRAM: 8192KiB 16-bit @ 25MT/s (CL-2 CWL-2) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Switching SDRAM to hardware control. Memtest at 0x40000000 (2MiB)... Write: 0x40000000-0x40200000 2MiB Read: 0x40000000-0x40200000 2MiB Memtest OK Memspeed at 0x40000000 (2MiB)... Write speed: 5MiB/s Read speed: 6MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex> mem_list Available memory regions: ROM 0x00000000 0x6000 SRAM 0x01000000 0x1000 SPIFLASH 0x80000000 0x1000000 MAIN_RAM 0x40000000 0x800000 CSR 0x82000000 0x10000 litex> mem_test 0x40000000 0x800000 Memtest at 0x40000000 (8MiB)... Write: 0x40000000-0x40800000 8MiB Read: 0x40000000-0x40800000 8MiB Memtest OK litex> --- litex_boards/platforms/tec0117.py | 23 +++++++------- litex_boards/targets/tec0117.py | 50 +++++++++++++++++++++++-------- 2 files changed, 49 insertions(+), 24 deletions(-) diff --git a/litex_boards/platforms/tec0117.py b/litex_boards/platforms/tec0117.py index 6ffeef2..37d3241 100644 --- a/litex_boards/platforms/tec0117.py +++ b/litex_boards/platforms/tec0117.py @@ -15,8 +15,9 @@ from litex.build.openfpgaloader import OpenFPGALoader _io = [ # Clk / Rst - ("clk12", 0, Pins("35"), IOStandard("LVCMOS33")), - ("rst", 0, Pins("77"), IOStandard("LVCMOS33")), + ("clk12", 0, Pins("35"), IOStandard("LVCMOS33")), + ("clk100", 0, Pins("63"), IOStandard("LVCMOS33")), + ("rst_n", 0, Pins("77"), IOStandard("LVCMOS33")), # Leds ("user_led", 0, Pins("86"), IOStandard("LVCMOS33")), @@ -31,7 +32,7 @@ _io = [ # Serial ("serial", 0, Subsignal("tx", Pins("15"), IOStandard("LVCMOS33")), - Subsignal("rx", Pins("16"), IOStandard("LVCMOS33")) + Subsignal("rx", Pins("16"), IOStandard("LVCMOS33")), ), # SPIFlash @@ -59,15 +60,15 @@ _io = [ ), # SDRAM (embedded in SIP, requires specific IO naming) - ("O_sdram_clk", 0, Pins(1), IOStandard("LVCMOS33")), - ("O_sdram_cke", 0, Pins(1), IOStandard("LVCMOS33")), - ("O_sdram_cs_n", 0, Pins(1), IOStandard("LVCMOS33")), - ("O_sdram_cas_n", 0, Pins(1), IOStandard("LVCMOS33")), - ("O_sdram_ras_n", 0, Pins(1), IOStandard("LVCMOS33")), - ("O_sdram_we_n", 0, Pins(1), IOStandard("LVCMOS33")), - ("O_sdram_dqm", 0, Pins(2), IOStandard("LVCMOS33")), + ("O_sdram_clk", 0, Pins(1), IOStandard("LVCMOS33")), + ("O_sdram_cke", 0, Pins(1), IOStandard("LVCMOS33")), + ("O_sdram_cs_n", 0, Pins(1), IOStandard("LVCMOS33")), + ("O_sdram_cas_n", 0, Pins(1), IOStandard("LVCMOS33")), + ("O_sdram_ras_n", 0, Pins(1), IOStandard("LVCMOS33")), + ("O_sdram_wen_n", 0, Pins(1), IOStandard("LVCMOS33")), + ("O_sdram_dqm", 0, Pins(2), IOStandard("LVCMOS33")), ("O_sdram_addr", 0, Pins(12), IOStandard("LVCMOS33")), - ("O_sdram_ba", 0, Pins(2), IOStandard("LVCMOS33")), + ("O_sdram_ba", 0, Pins(2), IOStandard("LVCMOS33")), ("IO_sdram_dq", 0, Pins(16), IOStandard("LVCMOS33")), ] diff --git a/litex_boards/targets/tec0117.py b/litex_boards/targets/tec0117.py index a22ec39..7fbda89 100755 --- a/litex_boards/targets/tec0117.py +++ b/litex_boards/targets/tec0117.py @@ -22,15 +22,41 @@ from litex.soc.cores.led import LedChaser from litex_boards.platforms import tec0117 -from litedram.modules import M12L64322A # FIXME +from litedram.modules import MT48LC4M16 # FIXME: use EtronTech reference. from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY kB = 1024 mB = 1024*kB +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.rst = Signal() + self.clock_domains.cd_sys = ClockDomain() + + # # # + + # Clk / Rst + clk100 = platform.request("clk100") + rst_n = platform.request("rst_n") + + # Generate 25Mhz sys_clk_freq clock from 100MHz input clock, FIXME: use PLL. + assert sys_clk_freq == 25e6 + self.clock_domains.cd_clk100 = ClockDomain() + self.comb += self.cd_clk100.clk.eq(clk100) + count = Signal(2) + self.sync.clk100 += count.eq(count + 1) + clk50 = count[0] + clk25 = count[1] + self.comb += self.cd_sys.clk.eq(clk25) + self.comb += self.cd_sys.rst.eq(~rst_n | self.rst) # FIXME: use AsyncResetSynchronizer + +# BaseSoC ------------------------------------------------------------------------------------------ + class BaseSoC(SoCCore): mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}} - def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), with_sdram=False, sdram_rate="1:1", **kwargs): + def __init__(self, bios_flash_offset, sys_clk_freq=int(25e6), sdram_rate="1:1", **kwargs): platform = tec0117.Platform() # Use custom default configuration to fit in LittleBee. @@ -49,7 +75,7 @@ class BaseSoC(SoCCore): **kwargs) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = CRG(platform.request("clk12"), ~platform.request("rst")) + self.submodules.crg = _CRG(platform, sys_clk_freq) # SPI Flash -------------------------------------------------------------------------------- self.add_spi_flash(mode="1x", dummy_cycles=8) @@ -62,8 +88,8 @@ class BaseSoC(SoCCore): # linker = True) #) - # SDR SDRAM (WIP) -------------------------------------------------------------------------- - if with_sdram: + # SDR SDRAM -------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: class SDRAMPads: def __init__(self): self.clk = platform.request("O_sdram_clk") @@ -71,25 +97,23 @@ class BaseSoC(SoCCore): self.cs_n = platform.request("O_sdram_cs_n") self.cas_n = platform.request("O_sdram_cas_n") self.ras_n = platform.request("O_sdram_ras_n") - self.we_n = platform.request("O_sdram_we_n") + self.we_n = platform.request("O_sdram_wen_n") self.dm = platform.request("O_sdram_dqm") self.a = platform.request("O_sdram_addr") self.ba = platform.request("O_sdram_ba") self.dq = platform.request("IO_sdram_dq") sdram_pads = SDRAMPads() - self.comb += sdram_pads.clk.eq(~ClockSignal("sys")) + self.comb += sdram_pads.clk.eq(~ClockSignal("sys")) # FIXME: use phase shift from PLL. sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, - module = M12L64322A(sys_clk_freq, sdram_rate), + module = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME. origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x10000000), - l2_cache_size = 0, - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + l2_cache_size = 128, + l2_cache_min_data_width = 256, ) # Leds ------------------------------------------------------------------------------------- @@ -165,7 +189,7 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--bios-flash-offset", default=0x80000, help="BIOS offset in SPI Flash (0x00000 default)") parser.add_argument("--flash", action="store_true", help="Flash Bitstream and BIOS") - parser.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency (default: 12MHz)") + parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency (default: 12MHz)") builder_args(parser) soc_core_args(parser) args = parser.parse_args()