diff --git a/litex_boards/platforms/alientek_davincipro.py b/litex_boards/platforms/alientek_davincipro.py
index b0fdbad..212d854 100644
--- a/litex_boards/platforms/alientek_davincipro.py
+++ b/litex_boards/platforms/alientek_davincipro.py
@@ -314,7 +314,7 @@ class Platform(Xilinx7SeriesPlatform):
         assert variant in ["a7-35", "a7-100"]
         kgates = variant.split("-")[-1]
         self.kgates = kgates
-        Xilinx7SeriesPlatform.__init__(self, f"xc7a{kgates}t-fgg484-1", _io, _connectors, toolchain=toolchain)
+        Xilinx7SeriesPlatform.__init__(self, f"xc7a{kgates}t-fgg484-2", _io, _connectors, toolchain=toolchain)
         self.toolchain.bitstream_commands = \
             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
              "set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]",
diff --git a/litex_boards/targets/alientek_davincipro.py b/litex_boards/targets/alientek_davincipro.py
index f59a3e5..d5a425b 100644
--- a/litex_boards/targets/alientek_davincipro.py
+++ b/litex_boards/targets/alientek_davincipro.py
@@ -55,7 +55,7 @@ class _CRG(LiteXModule):
         rst   = ~platform.request("cpu_reset") if with_rst else 0
 
         # PLL.
-        self.pll = pll = S7PLL(speedgrade=-1)
+        self.pll = pll = S7PLL(speedgrade=-2)
         self.comb += pll.reset.eq(rst | self.rst)
         pll.register_clkin(clk50, 50e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
@@ -71,7 +71,7 @@ class _CRG(LiteXModule):
             self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
         if with_hdmi:
-            self.submodules.pll2 = pll2 = S7MMCM(speedgrade=-1)
+            self.submodules.pll2 = pll2 = S7MMCM(speedgrade=-2)
             self.comb += pll2.reset.eq(rst | self.rst)
             pll2.register_clkin(clk50, 50e6)
             pll2.create_clkout(self.cd_hdmi,   25e6,  margin=0)