diff --git a/litex_boards/targets/kosagi_netv2.py b/litex_boards/targets/kosagi_netv2.py
index 7deec15..781975e 100755
--- a/litex_boards/targets/kosagi_netv2.py
+++ b/litex_boards/targets/kosagi_netv2.py
@@ -101,7 +101,7 @@ class BaseSoC(SoCCore):
             self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
                 data_width = 128,
                 bar0_size  = 0x20000)
-            self.add_pcie(phy=self.pcie_phy, ndmas=1, max_pending_requests=2)
+            self.add_pcie(phy=self.pcie_phy, ndmas=1)
 
         # Leds -------------------------------------------------------------------------------------
         self.submodules.leds = LedChaser(
diff --git a/litex_boards/targets/numato_tagus.py b/litex_boards/targets/numato_tagus.py
index 153c80e..8318fe9 100755
--- a/litex_boards/targets/numato_tagus.py
+++ b/litex_boards/targets/numato_tagus.py
@@ -89,7 +89,7 @@ class BaseSoC(SoCCore):
         # PCIe -------------------------------------------------------------------------------------
         if with_pcie:
             self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
-                data_width = 128,
+                data_width = 64,
                 bar0_size  = 0x20000)
             self.add_pcie(phy=self.pcie_phy, ndmas=1)
 
diff --git a/litex_boards/targets/rhsresearchllc_litefury.py b/litex_boards/targets/rhsresearchllc_litefury.py
index 4131439..fb4de7f 100755
--- a/litex_boards/targets/rhsresearchllc_litefury.py
+++ b/litex_boards/targets/rhsresearchllc_litefury.py
@@ -88,7 +88,7 @@ class BaseSoC(SoCCore):
         # PCIe -------------------------------------------------------------------------------------
         if with_pcie:
             self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
-                data_width = 64,
+                data_width = 128,
                 bar0_size  = 0x20000)
             self.add_pcie(phy=self.pcie_phy, ndmas=1)
 
diff --git a/litex_boards/targets/sqrl_fk33.py b/litex_boards/targets/sqrl_fk33.py
index f5f7454..c1bc0cb 100755
--- a/litex_boards/targets/sqrl_fk33.py
+++ b/litex_boards/targets/sqrl_fk33.py
@@ -62,7 +62,6 @@ class BaseSoC(SoCCore):
             self.submodules.pcie_phy = USPHBMPCIEPHY(platform, platform.request("pcie_x4"),
                 data_width = 128,
                 bar0_size  = 0x20000)
-            platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
 
             # Endpoint
             self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)