From 7d89aa0fe9b0f6b0277b5a565d3f44ff117f9977 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Sat, 30 Mar 2024 20:24:01 +0700 Subject: [PATCH] qmtech altera boards: sdram io properties for more speed --- litex_boards/platforms/qmtech_10cl006.py | 7 ++++++- litex_boards/platforms/qmtech_5cefa2.py | 7 ++++++- litex_boards/platforms/qmtech_5cefa5.py | 7 ++++++- litex_boards/platforms/qmtech_ep4cex5.py | 7 ++++++- litex_boards/platforms/qmtech_ep4cgx150.py | 7 ++++++- litex_boards/targets/qmtech_5cefa5.py | 2 +- litex_boards/targets/qmtech_ep4cgx150.py | 2 +- 7 files changed, 32 insertions(+), 7 deletions(-) diff --git a/litex_boards/platforms/qmtech_10cl006.py b/litex_boards/platforms/qmtech_10cl006.py index c75d978..5c6c7cb 100644 --- a/litex_boards/platforms/qmtech_10cl006.py +++ b/litex_boards/platforms/qmtech_10cl006.py @@ -42,8 +42,13 @@ _io = [ Subsignal("we_n", Pins("P6")), Subsignal("dq", Pins( "K5 L3 L4 K6 N3 M6 P3 N5", - "N2 N1 L1 L2 K1 K2 J1 J2")), + "N2 N1 L1 L2 K1 K2 J1 J2"), + Misc("FAST_OUTPUT_ENABLE_REGISTER ON"), + Misc("FAST_INPUT_REGISTER ON")), Subsignal("dm", Pins("N6 P1")), + Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), + Misc("FAST_OUTPUT_REGISTER ON"), + Misc("ALLOW_SYNCH_CTRL_USAGE OFF"), IOStandard("3.3-V LVTTL") ), ] diff --git a/litex_boards/platforms/qmtech_5cefa2.py b/litex_boards/platforms/qmtech_5cefa2.py index 04a12b9..24fca66 100644 --- a/litex_boards/platforms/qmtech_5cefa2.py +++ b/litex_boards/platforms/qmtech_5cefa2.py @@ -42,8 +42,13 @@ _io = [ Subsignal("we_n", Pins("W9")), Subsignal("dq", Pins( "AA12 Y11 AA10 AB10 Y10 AA9 AB8 AA8", - " U10 T10 U11 R12 U12 P12 R10 R11")), + " U10 T10 U11 R12 U12 P12 R10 R11"), + Misc("FAST_OUTPUT_ENABLE_REGISTER ON"), + Misc("FAST_INPUT_REGISTER ON")), Subsignal("dm", Pins("AB7 V10")), + Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), + Misc("FAST_OUTPUT_REGISTER ON"), + Misc("ALLOW_SYNCH_CTRL_USAGE OFF"), IOStandard("3.3-V LVTTL") ), ] diff --git a/litex_boards/platforms/qmtech_5cefa5.py b/litex_boards/platforms/qmtech_5cefa5.py index b044670..50e9252 100644 --- a/litex_boards/platforms/qmtech_5cefa5.py +++ b/litex_boards/platforms/qmtech_5cefa5.py @@ -44,8 +44,13 @@ _io = [ Subsignal("we_n", Pins("U20")), Subsignal("dq", Pins( "AA22 AB22 Y22 Y21 W22 W21 V21 U22 M21 M22 T22 R21 R22 P22 N20 N21 ", - "K22 K21 J22 J21 H21 G22 G21 F22 E22 E20 D22 D21 C21 B22 A22 B21")), + "K22 K21 J22 J21 H21 G22 G21 F22 E22 E20 D22 D21 C21 B22 A22 B21"), + Misc("FAST_OUTPUT_ENABLE_REGISTER ON"), + Misc("FAST_INPUT_REGISTER ON")), Subsignal("dm", Pins("U21 L22 K20 E21")), + Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), + Misc("FAST_OUTPUT_REGISTER ON"), + Misc("ALLOW_SYNCH_CTRL_USAGE OFF"), IOStandard("3.3-V LVCMOS") ), ] diff --git a/litex_boards/platforms/qmtech_ep4cex5.py b/litex_boards/platforms/qmtech_ep4cex5.py index 4ad26f8..677bc92 100644 --- a/litex_boards/platforms/qmtech_ep4cex5.py +++ b/litex_boards/platforms/qmtech_ep4cex5.py @@ -43,8 +43,13 @@ _io = [ Subsignal("we_n", Pins("AB4")), Subsignal("dq", Pins( "AA10 AB9 AA9 AB8 AA8 AB7 AA7 AB5", - "Y7 W8 Y8 V9 V10 Y10 W10 V11")), + "Y7 W8 Y8 V9 V10 Y10 W10 V11"), + Misc("FAST_OUTPUT_ENABLE_REGISTER ON"), + Misc("FAST_INPUT_REGISTER ON")), Subsignal("dm", Pins("AA5 W7")), + Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), + Misc("FAST_OUTPUT_REGISTER ON"), + Misc("ALLOW_SYNCH_CTRL_USAGE OFF"), IOStandard("3.3-V LVTTL") ), ] diff --git a/litex_boards/platforms/qmtech_ep4cgx150.py b/litex_boards/platforms/qmtech_ep4cgx150.py index bc87a17..b79a11b 100644 --- a/litex_boards/platforms/qmtech_ep4cgx150.py +++ b/litex_boards/platforms/qmtech_ep4cgx150.py @@ -43,8 +43,13 @@ _io = [ Subsignal("we_n", Pins("G25")), Subsignal("dq", Pins( "B25 B26 C25 C26 D25 D26 E25 E26", - "H23 G24 G22 F24 F23 E24 D24 C24")), + "H23 G24 G22 F24 F23 E24 D24 C24"), + Misc("FAST_OUTPUT_ENABLE_REGISTER ON"), + Misc("FAST_INPUT_REGISTER ON")), Subsignal("dm", Pins("F26 H24")), + Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), + Misc("FAST_OUTPUT_REGISTER ON"), + Misc("ALLOW_SYNCH_CTRL_USAGE OFF"), IOStandard("3.3-V LVTTL") ), ] diff --git a/litex_boards/targets/qmtech_5cefa5.py b/litex_boards/targets/qmtech_5cefa5.py index bf534fa..0189164 100755 --- a/litex_boards/targets/qmtech_5cefa5.py +++ b/litex_boards/targets/qmtech_5cefa5.py @@ -75,7 +75,7 @@ class _CRG(LiteXModule): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=80e6, with_daughterboard=False, + def __init__(self, sys_clk_freq=95e6, with_daughterboard=False, with_ethernet = False, with_etherbone = False, eth_ip = "192.168.1.50", diff --git a/litex_boards/targets/qmtech_ep4cgx150.py b/litex_boards/targets/qmtech_ep4cgx150.py index b64c952..c0bf1f4 100755 --- a/litex_boards/targets/qmtech_ep4cgx150.py +++ b/litex_boards/targets/qmtech_ep4cgx150.py @@ -136,7 +136,7 @@ class BaseSoC(SoCCore): def main(): from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=qmtech_ep4cgx150.Platform, description="LiteX SoC on QMTECH EP4CE15.") - parser.add_target_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.") + parser.add_target_argument("--sys-clk-freq", default=90e6, type=float, help="System clock frequency.") parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).") parser.add_target_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.") ethopts = parser.target_group.add_mutually_exclusive_group()