From 7da8628fba26ec9dec0e74435cd54804f9dc3abb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 28 Oct 2020 19:09:06 +0100 Subject: [PATCH] targets/kc705: switch SATA to gen2. --- litex_boards/targets/kc705.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index 37fc2a0..a20f940 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -117,7 +117,7 @@ class BaseSoC(SoCCore): self.submodules.sata_phy = LiteSATAPHY(platform.device, refclk = sata_refclk, pads = platform.request("sfp"), - gen = "gen1", + gen = "gen2", clk_freq = sys_clk_freq, data_width = 16) @@ -137,8 +137,8 @@ class BaseSoC(SoCCore): self.add_csr("sata_block2mem") # Timing constraints - platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/75e6) - platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/75e6) + platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/150e6) + platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/150e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.sata_phy.crg.cd_sata_tx.clk,