From 7f26f3940f78fb804fa3295ac79bec40e8e945f6 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 3 Sep 2024 16:01:51 +0200 Subject: [PATCH] efinix_trion_t120_bga576_dev_kit.py: fixed/rewire rx_ctl/tx_ctl (not compatible with DDIO mode), added message at build time --- .../platforms/efinix_trion_t120_bga576_dev_kit.py | 6 ++++-- litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py | 9 +++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py index 6f258e1..81b7f6f 100644 --- a/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py +++ b/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py @@ -66,9 +66,11 @@ _io = [ ), ("eth", 0, - Subsignal("rx_ctl", Pins("F24")), + #Subsignal("rx_ctl", Pins("F24")), # Can't be used as DDIO + Subsignal("rx_ctl", Pins("M22")), # A wire must be soldered between R120 and R174 Subsignal("rx_data", Pins("J20 K20 J19 H20")), - Subsignal("tx_ctl", Pins("G24")), + #Subsignal("tx_ctl", Pins("G24")), # Can't be used as DDIO + Subsignal("tx_ctl", Pins("M21")), # A wire must be soldered between ETH1_TXEN (Pad 30) and R173 Subsignal("tx_data", Pins("L23 L22 K21 K19")), Subsignal("rst_n", Pins("F21")), Subsignal("mdc", Pins("G21")), diff --git a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py index b2a199a..a14a3c1 100755 --- a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py @@ -7,6 +7,8 @@ # Copyright (c) 2021 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause +import time + from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer @@ -94,6 +96,13 @@ class BaseSoC(SoCCore): if with_ethernet or with_etherbone: # Use board's Ethernet PHYs. if not eth_rmii_pmod: + msg = "\n" + msg += "rx_ctl/tx_ctl pads location aren't compatible with DDIO mode.\n" + msg += "An hardware modification must be done:\n" + msg += "- rx_ctl: a wire must be soldered between R120 and R174\n" + msg += "- tx_ctl: a wire must be soldered between ETH1_TXEN (Pad 30) and R173\n" + print(msg) + time.sleep(2) self.ethphy = LiteEthPHYRGMII( platform = platform, clock_pads = platform.request("eth_clocks", eth_phy),