From f4a48e51d779b635af1b2719d29f53d85d3adb8e Mon Sep 17 00:00:00 2001 From: Joseph Faye <31924862+jwfaye@users.noreply.github.com> Date: Wed, 16 Mar 2022 15:37:02 +0100 Subject: [PATCH 1/2] add xilinx_zcu102 platform --- litex_boards/platforms/xilinx_zcu102.py | 88 +++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 litex_boards/platforms/xilinx_zcu102.py diff --git a/litex_boards/platforms/xilinx_zcu102.py b/litex_boards/platforms/xilinx_zcu102.py new file mode 100644 index 0000000..4123724 --- /dev/null +++ b/litex_boards/platforms/xilinx_zcu102.py @@ -0,0 +1,88 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2022 FAYE Joseph +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform, VivadoProgrammer + + +# IOs ------------------------------------ + +_io = [ + # Clk / Rst + ("clk125", 0, + Subsignal("p", Pins("G21"), IOStandard("LVDS")), + Subsignal("n", Pins("F21"), IOStandard("LVDS")), + ), + ("clk300", 0, + Subsignal("p", Pins("AL8"), IOStandard("DIFF_SSTL12_DCI")), + Subsignal("n", Pins("AL7"), IOStandard("DIFF_SSTL12_DCI")), + ), + ("cpu_reset", 0, Pins("AM13"), IOStandard("LVCMOS33")), + + # Leds + ("user_led", 0, Pins("AG14"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("AF13"), IOStandard("LVCMOS33")), + ("user_led", 2, Pins("AE13"), IOStandard("LVCMOS33")), + ("user_led", 3, Pins("AJ14"), IOStandard("LVCMOS33")), + ("user_led", 4, Pins("AJ15"), IOStandard("LVCMOS33")), + ("user_led", 5, Pins("AH13"), IOStandard("LVCMOS33")) + ("user_led", 6, Pins("AH14"), IOStandard("LVCMOS33")) + ("user_led", 7, Pins("AL12"), IOStandard("LVCMOS33")) + + # Buttons + ("user_btn", 0, Pins("AG15"), IOStandard("LVCMOS33")), + ("user_btn", 1, Pins("AE14"), IOStandard("LVCMOS33")), + ("user_btn", 2, Pins("AF15"), IOStandard("LVCMOS33")), + ("user_btn", 3, Pins("AE15"), IOStandard("LVCMOS33")), + ("user_btn", 3, Pins("AG13"), IOStandard("LVCMOS33")), + + # Switches + ("user_dip", 0, Pins("AN14"), IOStandard("LVCMOS33")), + ("user_dip", 1, Pins("AP14"), IOStandard("LVCMOS33")), + ("user_dip", 2, Pins("AM14"), IOStandard("LVCMOS33")), + ("user_dip", 3, Pins("AN13"), IOStandard("LVCMOS33")), + ("user_dip", 4, Pins("AN12"), IOStandard("LVCMOS33")), + ("user_dip", 5, Pins("AP12"), IOStandard("LVCMOS33")), + ("user_dip", 6, Pins("AL13"), IOStandard("LVCMOS33")), + ("user_dip", 7, Pins("AK13"), IOStandard("LVCMOS33")), + + + # Serial + ("serial", 0, + Subsignal("cts", Pins("E12")), + Subsignal("rts", Pins("D12")), + Subsignal("tx", Pins("E13")), + Subsignal("rx", Pins("F13")), + IOStandard("LVCMOS18") + ), + + # I2C + ("i2c", 0, + Subsignal("sda", Pins("J11")), + Subsignal("scl", Pins("J10")), + IOStandard("LVCMOS33") + ), +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(XilinxPlatform): + default_clk_name = "clk125" + default_clk_period = 1e9/125e6 + + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xczu9eg-ffvb1156-2-i", _io, toolchain=toolchain) + + def create_programmer(self): + return VivadoProgrammer() + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6) + self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/300e6) + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]") + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]") + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]") \ No newline at end of file From adbcc2e547ef54e44a9f06add4c855f368254753 Mon Sep 17 00:00:00 2001 From: Joseph Faye <31924862+jwfaye@users.noreply.github.com> Date: Wed, 16 Mar 2022 15:55:37 +0100 Subject: [PATCH 2/2] add zcu102 target file --- litex_boards/targets/xilinx_zcu102.py | 69 +++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 litex_boards/targets/xilinx_zcu102.py diff --git a/litex_boards/targets/xilinx_zcu102.py b/litex_boards/targets/xilinx_zcu102.py new file mode 100644 index 0000000..c555f0e --- /dev/null +++ b/litex_boards/targets/xilinx_zcu102.py @@ -0,0 +1,69 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2022 Joseph FAYE +# SPDX-License-Identifier: BSD-2-Clause + +import os +import argparse +import importlib + +from migen import * + +from litex_boards.platforms import xilinx_zcu102 as zcu102 + +from litex.build.io import CRG + +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * + +from litex.soc.cores.led import LedChaser + + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq, with_ethernet=False, with_led_chaser=True, **kwargs): + platform = zcu102.Platform() + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident="LiteX SoC on ZCU102", + **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = CRG(sys_clk_freq) + + # Leds ------------------------------------------------------------------------------------- + try: + if with_led_chaser: + self.submodules.leds = LedChaser( + pads=platform.request_all("user_led"), + sys_clk_freq=sys_clk_freq) + except: + pass + + +# Build -------------------------------------------------------------------------------------------- +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on ZCU102") + parser.add_argument("--build", action="store_true", help="Build bitstream.") + parser.add_argument("--load", action="store_true", help="Load bitstream.") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock generator.") + builder_args(parser) + soc_core_args(parser) + args = parser.parse_args() + + soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_core_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build(run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) + + +if __name__ == "__main__": + main() \ No newline at end of file