From 805a520b5a533b020de8b813a47ae32b5422dbe9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 18 Jun 2024 09:14:08 +0200 Subject: [PATCH] litex_acorn_baseboard_mini: Fix and test PCIe Gen2 X1 with it. --- litex_boards/platforms/sqrl_acorn.py | 10 +++++----- litex_boards/targets/litex_acorn_baseboard_mini.py | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/litex_boards/platforms/sqrl_acorn.py b/litex_boards/platforms/sqrl_acorn.py index 441a5ad..3ee3c12 100644 --- a/litex_boards/platforms/sqrl_acorn.py +++ b/litex_boards/platforms/sqrl_acorn.py @@ -43,13 +43,13 @@ _io = [ # PCIe. ("pcie_clkreq_n", 0, Pins("G1"), IOStandard("LVCMOS33")), ("pcie_x1_baseboard", 0, - Subsignal("rst_n", Pins("A15"), IOStandard("LVCMOS15"), Misc("PULLUP=TRUE")), + Subsignal("rst_n", Pins("J1"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), Subsignal("clk_p", Pins("F6")), Subsignal("clk_n", Pins("E6")), - Subsignal("rx_p", Pins("B8")), - Subsignal("rx_n", Pins("A8")), - Subsignal("tx_p", Pins("B4")), - Subsignal("tx_n", Pins("A4")), + Subsignal("rx_p", Pins("D9")), + Subsignal("rx_n", Pins("C9")), + Subsignal("tx_p", Pins("D7")), + Subsignal("tx_n", Pins("C7")), ), ("pcie_x4", 0, Subsignal("rst_n", Pins("J1"), IOStandard("LVCMOS15"), Misc("PULLUP=TRUE")), diff --git a/litex_boards/targets/litex_acorn_baseboard_mini.py b/litex_boards/targets/litex_acorn_baseboard_mini.py index 87de2be..f30bde1 100755 --- a/litex_boards/targets/litex_acorn_baseboard_mini.py +++ b/litex_boards/targets/litex_acorn_baseboard_mini.py @@ -142,7 +142,7 @@ class BaseSoC(SoCCore): bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) platform.toolchain.pre_placement_commands.append("reset_property LOC [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]") - platform.toolchain.pre_placement_commands.append("set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]") + platform.toolchain.pre_placement_commands.append("set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]") # Ethernet / SATA RefClk/Shared-QPLL -------------------------------------------------------