diff --git a/litex_boards/partner/targets/aller.py b/litex_boards/partner/targets/aller.py
index 27d3368..9a4dae7 100755
--- a/litex_boards/partner/targets/aller.py
+++ b/litex_boards/partner/targets/aller.py
@@ -90,8 +90,6 @@ class PCIeSoC(SoCSDRAM):
         # PCIe -------------------------------------------------------------------------------------
         # pcie phy
         self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
-        self.pcie_phy.cd_pcie.clk.attr.add("keep")
-        platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
         platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
         self.add_csr("pcie_phy")
 
diff --git a/litex_boards/partner/targets/nereid.py b/litex_boards/partner/targets/nereid.py
index 99eaad6..5f6df91 100755
--- a/litex_boards/partner/targets/nereid.py
+++ b/litex_boards/partner/targets/nereid.py
@@ -89,8 +89,6 @@ class PCIeSoC(SoCSDRAM):
         # PCIe -------------------------------------------------------------------------------------
         # pcie phy
         self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
-        self.pcie_phy.cd_pcie.clk.attr.add("keep")
-        platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
         platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
         self.add_csr("pcie_phy")
 
diff --git a/litex_boards/partner/targets/tagus.py b/litex_boards/partner/targets/tagus.py
index ae1f132..5fbaa0b 100755
--- a/litex_boards/partner/targets/tagus.py
+++ b/litex_boards/partner/targets/tagus.py
@@ -91,8 +91,6 @@ class PCIeSoC(SoCSDRAM):
         # PCIe -------------------------------------------------------------------------------------
         # pcie phy
         self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
-        self.pcie_phy.cd_pcie.clk.attr.add("keep")
-        platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
         platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
         self.add_csr("pcie_phy")