From 814e7630e4b9092b362b56ee104eb45dd07fc78d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 13 Oct 2020 12:10:29 +0200 Subject: [PATCH] targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it. --- litex_boards/targets/ac701.py | 4 ++-- litex_boards/targets/acorn_cle_215.py | 6 +++--- litex_boards/targets/aller.py | 6 +++--- litex_boards/targets/alveo_u250.py | 8 ++++---- litex_boards/targets/arty.py | 6 +++--- litex_boards/targets/arty_s7.py | 6 +++--- litex_boards/targets/genesys2.py | 6 +++--- litex_boards/targets/kc705.py | 6 +++--- litex_boards/targets/kcu105.py | 8 ++++---- litex_boards/targets/kx2.py | 6 +++--- litex_boards/targets/logicbone.py | 6 ++++-- litex_boards/targets/mercury_xu5.py | 8 ++++---- litex_boards/targets/mimas_a7.py | 6 +++--- litex_boards/targets/nereid.py | 6 +++--- litex_boards/targets/netv2.py | 6 +++--- litex_boards/targets/nexys4ddr.py | 6 +++--- litex_boards/targets/nexys_video.py | 6 +++--- litex_boards/targets/tagus.py | 6 +++--- litex_boards/targets/vc707.py | 6 +++--- litex_boards/targets/vcu118.py | 8 ++++---- litex_boards/targets/xcu1525.py | 10 +++++----- litex_boards/targets/zcu104.py | 8 ++++---- 22 files changed, 73 insertions(+), 71 deletions(-) diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py index 34adc2d..12b3be1 100755 --- a/litex_boards/targets/ac701.py +++ b/litex_boards/targets/ac701.py @@ -45,9 +45,9 @@ class _CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py index 1569707..2febf73 100755 --- a/litex_boards/targets/acorn_cle_215.py +++ b/litex_boards/targets/acorn_cle_215.py @@ -55,7 +55,7 @@ class CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # Clk/Rst clk200 = platform.request("clk200") @@ -66,9 +66,9 @@ class CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ----------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py index 418323d..57be2c2 100755 --- a/litex_boards/targets/aller.py +++ b/litex_boards/targets/aller.py @@ -39,7 +39,7 @@ class CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # Clk/Rst clk100 = platform.request("clk100") @@ -50,9 +50,9 @@ class CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ----------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py index 3c78841..b6ca6e1 100755 --- a/litex_boards/targets/alveo_u250.py +++ b/litex_boards/targets/alveo_u250.py @@ -36,7 +36,7 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk500 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # @@ -44,7 +44,7 @@ class _CRG(Module): self.comb += pll.reset.eq(0) # FIXME pll.register_clkin(platform.request("clk300", 0), 300e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_clk500, 500e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 500e6, with_reset=False) self.specials += [ Instance("BUFGCE_DIV", name="main_bufgce_div", @@ -52,10 +52,10 @@ class _CRG(Module): i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), Instance("BUFGCE", name="main_bufgce", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_clk500, ~pll.locked), + AsyncResetSynchronizer(self.cd_idelay, ~pll.locked), ] - self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk500, cd_sys=self.cd_sys) + self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py index 745d5a6..e5a0727 100755 --- a/litex_boards/targets/arty.py +++ b/litex_boards/targets/arty.py @@ -32,7 +32,7 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() self.clock_domains.cd_eth = ClockDomain() # # # @@ -43,10 +43,10 @@ class _CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) pll.create_clkout(self.cd_eth, 25e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk) diff --git a/litex_boards/targets/arty_s7.py b/litex_boards/targets/arty_s7.py index c166c14..192b63d 100755 --- a/litex_boards/targets/arty_s7.py +++ b/litex_boards/targets/arty_s7.py @@ -32,7 +32,7 @@ class _CRG(Module): self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # @@ -43,9 +43,9 @@ class _CRG(Module): pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py index 74b4611..b2ea77d 100755 --- a/litex_boards/targets/genesys2.py +++ b/litex_boards/targets/genesys2.py @@ -30,7 +30,7 @@ class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # @@ -39,9 +39,9 @@ class _CRG(Module): pll.register_clkin(platform.request("clk200"), 200e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index 11d0026..ea2e6b2 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -32,7 +32,7 @@ class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # @@ -41,9 +41,9 @@ class _CRG(Module): pll.register_clkin(platform.request("clk200"), 200e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index 5217908..65fb8ed 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -31,7 +31,7 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() self.clock_domains.cd_eth = ClockDomain() # # # @@ -40,7 +40,7 @@ class _CRG(Module): self.comb += pll.reset.eq(platform.request("cpu_reset")) pll.register_clkin(platform.request("clk125"), 125e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_clk200, 200e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 200e6, with_reset=False) pll.create_clkout(self.cd_eth, 200e6) self.specials += [ @@ -49,10 +49,10 @@ class _CRG(Module): i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), Instance("BUFGCE", name="main_bufgce", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_clk200, ~pll.locked), + AsyncResetSynchronizer(self.cd_idelay, ~pll.locked), ] - self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk200, cd_sys=self.cd_sys) + self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/kx2.py b/litex_boards/targets/kx2.py index 575b5f9..ae31996 100755 --- a/litex_boards/targets/kx2.py +++ b/litex_boards/targets/kx2.py @@ -28,7 +28,7 @@ class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # @@ -37,9 +37,9 @@ class _CRG(Module): pll.register_clkin(platform.request("clk200"), 200e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index d791eb5..ac9fa59 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -93,8 +93,10 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, revision="rev0", device="45F", sdram_device="MT41K512M16", - with_ethernet=False, - sys_clk_freq=int(75e6), toolchain="trellis", **kwargs): + with_ethernet = False, + sys_clk_freq = int(75e6), + toolchain = "trellis", + **kwargs): platform = logicbone.Platform(revision=revision, device=device ,toolchain=toolchain) # Serial ----------------------------------------------------------------------------------- diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py index 0a99b3d..89803e2 100755 --- a/litex_boards/targets/mercury_xu5.py +++ b/litex_boards/targets/mercury_xu5.py @@ -30,7 +30,7 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk500 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # @@ -38,7 +38,7 @@ class _CRG(Module): pll.register_clkin(platform.request("clk100"), 100e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_clk500, 500e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 500e6, with_reset=False) self.specials += [ Instance("BUFGCE_DIV", name="main_bufgce_div", @@ -46,10 +46,10 @@ class _CRG(Module): i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), Instance("BUFGCE", name="main_bufgce", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_clk500, ~pll.locked), + AsyncResetSynchronizer(self.cd_idelay, ~pll.locked), ] - self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk500, cd_sys=self.cd_sys) + self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py index c8d6eec..26af0d1 100755 --- a/litex_boards/targets/mimas_a7.py +++ b/litex_boards/targets/mimas_a7.py @@ -33,7 +33,7 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # @@ -43,9 +43,9 @@ class _CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py index 54a03f9..1a72402 100755 --- a/litex_boards/targets/nereid.py +++ b/litex_boards/targets/nereid.py @@ -37,7 +37,7 @@ class CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # Clk/Rst clk100 = platform.request("clk100") @@ -47,9 +47,9 @@ class CRG(Module): pll.register_clkin(clk100, 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ----------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py index 70c55ee..964130d 100755 --- a/litex_boards/targets/netv2.py +++ b/litex_boards/targets/netv2.py @@ -31,7 +31,7 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() self.clock_domains.cd_clk100 = ClockDomain() self.clock_domains.cd_eth = ClockDomain() @@ -42,11 +42,11 @@ class _CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) pll.create_clkout(self.cd_clk100, 100e6) pll.create_clkout(self.cd_eth, 50e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py index 7e795a7..fca79a6 100755 --- a/litex_boards/targets/nexys4ddr.py +++ b/litex_boards/targets/nexys4ddr.py @@ -31,7 +31,7 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() self.clock_domains.cd_eth = ClockDomain() # # # @@ -42,10 +42,10 @@ class _CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) pll.create_clkout(self.cd_eth, 50e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py index 4dcf5c8..c16d8d2 100755 --- a/litex_boards/targets/nexys_video.py +++ b/litex_boards/targets/nexys_video.py @@ -31,7 +31,7 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() self.clock_domains.cd_clk100 = ClockDomain() # # # @@ -42,10 +42,10 @@ class _CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) pll.create_clkout(self.cd_clk100, 100e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py index dc525aa..3212c75 100755 --- a/litex_boards/targets/tagus.py +++ b/litex_boards/targets/tagus.py @@ -39,7 +39,7 @@ class CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # Clk/Rst clk100 = platform.request("clk100") @@ -50,9 +50,9 @@ class CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ----------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py index 13706cc..0be2798 100755 --- a/litex_boards/targets/vc707.py +++ b/litex_boards/targets/vc707.py @@ -27,7 +27,7 @@ class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # @@ -36,9 +36,9 @@ class _CRG(Module): pll.register_clkin(platform.request("clk200"), 200e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py index 419457b..cf00272 100755 --- a/litex_boards/targets/vcu118.py +++ b/litex_boards/targets/vcu118.py @@ -30,7 +30,7 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk500 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # @@ -38,7 +38,7 @@ class _CRG(Module): self.comb += pll.reset.eq(platform.request("cpu_reset")) pll.register_clkin(platform.request("clk125"), 125e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_clk500, 500e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 500e6, with_reset=False) self.specials += [ Instance("BUFGCE_DIV", name="main_bufgce_div", @@ -46,10 +46,10 @@ class _CRG(Module): i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), Instance("BUFGCE", name="main_bufgce", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_clk500, ~pll.locked), + AsyncResetSynchronizer(self.cd_idelay, ~pll.locked), ] - self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk500, cd_sys=self.cd_sys) + self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py index 6f89966..6c68ffc 100755 --- a/litex_boards/targets/xcu1525.py +++ b/litex_boards/targets/xcu1525.py @@ -35,14 +35,14 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk500 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # self.submodules.pll = pll = USPMMCM(speedgrade=-2) pll.register_clkin(platform.request("clk300", ddram_channel), 300e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_clk500, 500e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 500e6, with_reset=False) self.specials += [ Instance("BUFGCE_DIV", name="main_bufgce_div", @@ -50,10 +50,10 @@ class _CRG(Module): i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), Instance("BUFGCE", name="main_bufgce", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_clk500, ~pll.locked), + AsyncResetSynchronizer(self.cd_idelay, ~pll.locked), ] - self.submodules.idelayctrl = USPIDELAYCTRL(cd_ref=self.cd_clk500, cd_sys=self.cd_sys) + self.submodules.idelayctrl = USPIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------ @@ -68,7 +68,7 @@ class BaseSoC(SoCCore): **kwargs) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq) + self.submodules.crg = _CRG(platform, sys_clk_freq, ddram_channel) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py index af15e74..74d554e 100755 --- a/litex_boards/targets/zcu104.py +++ b/litex_boards/targets/zcu104.py @@ -31,14 +31,14 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk500 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # self.submodules.pll = pll = USMMCM(speedgrade=-2) pll.register_clkin(platform.request("clk125"), 125e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_clk500, 500e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 500e6, with_reset=False) self.specials += [ Instance("BUFGCE_DIV", name="main_bufgce_div", @@ -46,10 +46,10 @@ class _CRG(Module): i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), Instance("BUFGCE", name="main_bufgce", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_clk500, ~pll.locked), + AsyncResetSynchronizer(self.cd_idelay, ~pll.locked), ] - self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk500, cd_sys=self.cd_sys) + self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------