diff --git a/litex_boards/targets/1bitsquared_icebreaker.py b/litex_boards/targets/1bitsquared_icebreaker.py
index bd87c8d..2ffc315 100755
--- a/litex_boards/targets/1bitsquared_icebreaker.py
+++ b/litex_boards/targets/1bitsquared_icebreaker.py
@@ -68,7 +68,6 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
     def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_led_chaser=True,
                  with_video_terminal=False, **kwargs):
         platform = icebreaker.Platform()
@@ -78,9 +77,6 @@ class BaseSoC(SoCCore):
         kwargs["integrated_sram_size"] = 0
         kwargs["integrated_rom_size"]  = 0
 
-        # Set CPU variant / reset address
-        kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
-
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
             ident          = "LiteX SoC on iCEBreaker",
@@ -112,10 +108,13 @@ class BaseSoC(SoCCore):
 
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
-            origin = self.mem_map["spiflash"] + bios_flash_offset,
+            origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
             size   = 32*kB,
             linker = True)
         )
+        # Set CPU reset address to ROM.
+        if hasattr(self.cpu, "set_reset_address"):
+            self.cpu.set_reset_address(self.bus.regions["rom"].origin)
 
         # Video ------------------------------------------------------------------------------------
         if with_video_terminal:
diff --git a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
index 15d21a9..9e6ff0e 100755
--- a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
+++ b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
@@ -65,7 +65,6 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
     def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), revision="v1", **kwargs):
         platform = icebreaker_bitsy.Platform(revision=revision)
 
@@ -73,9 +72,6 @@ class BaseSoC(SoCCore):
         kwargs["integrated_sram_size"] = 0
         kwargs["integrated_rom_size"]  = 0
 
-        # Set CPU variant / reset address
-        kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
-
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
             ident          = "LiteX SoC on iCEBreaker-bitsy",
@@ -107,10 +103,13 @@ class BaseSoC(SoCCore):
 
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
-            origin = self.mem_map["spiflash"] + bios_flash_offset,
+            origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
             size   = 32*kB,
             linker = True)
         )
+        # Set CPU reset address to ROM.
+        if hasattr(self.cpu, "set_reset_address"):
+            self.cpu.set_reset_address(self.bus.regions["rom"].origin)
 
 # Build --------------------------------------------------------------------------------------------
 
diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py
index 7dec526..392c098 100755
--- a/litex_boards/targets/kosagi_fomu.py
+++ b/litex_boards/targets/kosagi_fomu.py
@@ -68,7 +68,6 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
     def __init__(self, bios_flash_offset, spi_flash_module="AT25SF161", sys_clk_freq=int(12e6),
                  with_led_chaser=True, **kwargs):
         kwargs["uart_name"] = "usb_acm" # Enforce UART to USB-ACM
@@ -78,9 +77,6 @@ class BaseSoC(SoCCore):
         kwargs["integrated_sram_size"] = 0
         kwargs["integrated_rom_size"]  = 0
 
-        # Set CPU variant / reset address
-        kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
-
         # Serial -----------------------------------------------------------------------------------
         # FIXME: do proper install of ValentyUSB.
         os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
@@ -125,10 +121,13 @@ class BaseSoC(SoCCore):
 
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
-            origin = self.mem_map["spiflash"] + bios_flash_offset,
+            origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
             size   = 32*kB,
             linker = True)
         )
+        # Set CPU reset address to ROM.
+        if hasattr(self.cpu, "set_reset_address"):
+            self.cpu.set_reset_address(self.bus.regions["rom"].origin)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
diff --git a/litex_boards/targets/lattice_ice40up5k_evn.py b/litex_boards/targets/lattice_ice40up5k_evn.py
index d676ce3..9d67218 100755
--- a/litex_boards/targets/lattice_ice40up5k_evn.py
+++ b/litex_boards/targets/lattice_ice40up5k_evn.py
@@ -61,7 +61,6 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
     def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), with_led_chaser=True, **kwargs):
         platform = lattice_ice40up5k_evn.Platform()
 
@@ -69,9 +68,6 @@ class BaseSoC(SoCCore):
         kwargs["integrated_sram_size"] = 0
         kwargs["integrated_rom_size"]  = 0
 
-        # Set CPU variant / reset address
-        kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
-
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
             ident          = "LiteX SoC on Lattice iCE40UP5k EVN breakout board",
@@ -93,10 +89,13 @@ class BaseSoC(SoCCore):
 
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
-            origin = self.mem_map["spiflash"] + bios_flash_offset,
+            origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
             size   = 32*kB,
             linker = True)
         )
+        # Set CPU reset address to ROM.
+        if hasattr(self.cpu, "set_reset_address"):
+            self.cpu.set_reset_address(self.bus.regions["rom"].origin)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
diff --git a/litex_boards/targets/muselab_icesugar.py b/litex_boards/targets/muselab_icesugar.py
index f51420d..4e863aa 100755
--- a/litex_boards/targets/muselab_icesugar.py
+++ b/litex_boards/targets/muselab_icesugar.py
@@ -57,7 +57,6 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
     def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_led_chaser=True,
                  with_video_terminal=False, **kwargs):
         platform = muselab_icesugar.Platform()
@@ -66,9 +65,9 @@ class BaseSoC(SoCCore):
         kwargs["integrated_sram_size"] = 0
         kwargs["integrated_rom_size"]  = 0
 
-        # Set CPU variant / reset address
-        kwargs["cpu_variant"]  = "lite"
-        kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
+        # Set CPU variant
+        if kwargs.get("cpu_type", "vexriscv") == "vexriscv":
+            kwargs["cpu_variant"] = "lite"
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
@@ -90,10 +89,13 @@ class BaseSoC(SoCCore):
 
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
-            origin = self.mem_map["spiflash"] + bios_flash_offset,
+            origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
             size   = 32*kB,
             linker = True)
         )
+        # Set CPU reset address to ROM.
+        if hasattr(self.cpu, "set_reset_address"):
+            self.cpu.set_reset_address(self.bus.regions["rom"].origin)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
diff --git a/litex_boards/targets/myminieye_runber.py b/litex_boards/targets/myminieye_runber.py
index 2073c45..67b983d 100755
--- a/litex_boards/targets/myminieye_runber.py
+++ b/litex_boards/targets/myminieye_runber.py
@@ -40,7 +40,8 @@ class BaseSoC(SoCCore):
 
 
         # Disable CPU for now.
-        kwargs["cpu_type"]  = None
+        kwargs["cpu_type"] = None
+        kwargs["integrated_sram_size"] = 0
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
diff --git a/litex_boards/targets/qwertyembedded_beaglewire.py b/litex_boards/targets/qwertyembedded_beaglewire.py
index bf39b28..89b1bb7 100755
--- a/litex_boards/targets/qwertyembedded_beaglewire.py
+++ b/litex_boards/targets/qwertyembedded_beaglewire.py
@@ -66,7 +66,6 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
     def __init__(self, bios_flash_offset, sys_clk_freq=int(50e6), **kwargs):
         platform = beaglewire.Platform()
 
@@ -74,9 +73,6 @@ class BaseSoC(SoCCore):
         kwargs["integrated_rom_size"]  = 0
         kwargs["integrated_sram_size"] = 2*kB
 
-        # Set CPU reset address
-        kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
-
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
             ident          = "LiteX SoC on Beaglewire",
@@ -100,10 +96,13 @@ class BaseSoC(SoCCore):
 
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
-            origin = self.mem_map["spiflash"] + bios_flash_offset,
+            origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
             size   = 32*kB,
             linker = True)
         )
+        # Set CPU reset address to ROM.
+        if hasattr(self.cpu, "set_reset_address"):
+            self.cpu.set_reset_address(self.bus.regions["rom"].origin)
 
         # Leds -------------------------------------------------------------------------------------
         self.submodules.leds = LedChaser(
diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py
index 363316a..896aa1f 100755
--- a/litex_boards/targets/sipeed_tang_nano_4k.py
+++ b/litex_boards/targets/sipeed_tang_nano_4k.py
@@ -67,15 +67,13 @@ class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(27e6), with_hyperram=False, with_led_chaser=True, with_video_terminal=True, **kwargs):
         platform = tang_nano_4k.Platform()
 
-        if 'cpu_type' in kwargs and kwargs['cpu_type'] == 'gowin_emcu':
-            kwargs['with_uart'] = False  # CPU has own UART
-            kwargs['integrated_sram_size'] = 0  # SRAM is directly attached to CPU
-            kwargs["integrated_rom_size"] = 0  # boot flash directly attached to CPU
+        if "cpu_type" in kwargs and kwargs["cpu_type"] == "gowin_emcu":
+            kwargs["with_uart"]            = False # CPU has own UART
+            kwargs["integrated_sram_size"] = 0     # SRAM is directly attached to CPU
+            kwargs["integrated_rom_size"]  = 0     # boot flash directly attached to CPU
         else:
-            # Put BIOS in SPIFlash to save BlockRAMs.
-            self.mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
+            # Disable Integrated ROM
             kwargs["integrated_rom_size"] = 0
-            kwargs["cpu_reset_address"]   = self.mem_map["spiflash"] + 0
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
@@ -94,15 +92,18 @@ class BaseSoC(SoCCore):
         from litespi.opcodes import SpiNorFlashOpCodes as Codes
         self.add_spi_flash(mode="1x", module=W25Q32(Codes.READ_1_1_1), with_master=False)
 
-        if self.cpu_type == 'gowin_emcu':
-            self.cpu.connect_uart(platform.request('serial'))
+        if self.cpu_type == "gowin_emcu":
+            self.cpu.connect_uart(platform.request("serial"))
         else:
-        # Add ROM linker region --------------------------------------------------------------------
+            # Add ROM linker region --------------------------------------------------------------------
             self.bus.add_region("rom", SoCRegion(
-                origin = self.mem_map["spiflash"] + 0,
-                size   = 64*kB,
+                origin = self.bus.regions["spiflash"].origin,
+                size   = 32*kB,
                 linker = True)
             )
+            # Set CPU reset address to ROM.
+            if hasattr(self.cpu, "set_reset_address"):
+                self.cpu.set_reset_address(self.bus.regions["rom"].origin)
 
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
diff --git a/litex_boards/targets/tinyfpga_bx.py b/litex_boards/targets/tinyfpga_bx.py
index 7657918..6d40bdc 100755
--- a/litex_boards/targets/tinyfpga_bx.py
+++ b/litex_boards/targets/tinyfpga_bx.py
@@ -27,16 +27,12 @@ mB = 1024*kB
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
     def __init__(self, bios_flash_offset, sys_clk_freq=int(16e6), with_led_chaser=True, **kwargs):
         platform = tinyfpga_bx.Platform()
 
         # Disable Integrated ROM since too large for iCE40.
         kwargs["integrated_rom_size"]  = 0
 
-        # Set CPU variant / reset address
-        kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
-
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
             ident          = "LiteX SoC on TinyFPGA BX",
@@ -53,10 +49,13 @@ class BaseSoC(SoCCore):
 
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
-            origin = self.mem_map["spiflash"] + bios_flash_offset,
+            origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
             size   = 32*kB,
             linker = True)
         )
+        # Set CPU reset address to ROM.
+        if hasattr(self.cpu, "set_reset_address"):
+            self.cpu.set_reset_address(self.bus.regions["rom"].origin)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
diff --git a/litex_boards/targets/trenz_tec0117.py b/litex_boards/targets/trenz_tec0117.py
index 8fac0b4..b77e659 100755
--- a/litex_boards/targets/trenz_tec0117.py
+++ b/litex_boards/targets/trenz_tec0117.py
@@ -60,14 +60,12 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
     def __init__(self, bios_flash_offset=0x0000, sys_clk_freq=int(25e6), sdram_rate="1:1",
                  with_led_chaser=True, **kwargs):
         platform = tec0117.Platform()
 
-        # Put BIOS in SPIFlash to save BlockRAMs.
+        # Disable Integrated ROM.
         kwargs["integrated_rom_size"] = 0
-        kwargs["cpu_reset_address"]   = self.mem_map["spiflash"] + bios_flash_offset
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
@@ -85,10 +83,13 @@ class BaseSoC(SoCCore):
 
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
-            origin = self.mem_map["spiflash"] + bios_flash_offset,
-            size   = 64*kB,
+            origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
+            size   = 32*kB,
             linker = True)
         )
+        # Set CPU reset address to ROM.
+        if hasattr(self.cpu, "set_reset_address"):
+            self.cpu.set_reset_address(self.bus.regions["rom"].origin)
 
         # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
diff --git a/test/test_targets.py b/test/test_targets.py
index e18e449..08cbcf1 100644
--- a/test/test_targets.py
+++ b/test/test_targets.py
@@ -35,6 +35,7 @@ class TestTargets(unittest.TestCase):
         "efinix_xyloni_dev_kit",             # Reason: Require Efinity toolchain.
         "sipeed_tang_primer",                # Reason: Require Anlogic toolchain.
         "jungle_electronics_fireant",        # Reason: Require Efinity toolchain.
+        "qmtech_10cl006",                    # Readon: Needs to be fixed.
     ]
 
     # Build simple design for all platforms.