diff --git a/litex_boards/partner/platforms/hadbadge.py b/litex_boards/partner/platforms/hadbadge.py
index 022b5a2..a620459 100644
--- a/litex_boards/partner/platforms/hadbadge.py
+++ b/litex_boards/partner/platforms/hadbadge.py
@@ -208,7 +208,7 @@ class Platform(LatticePlatform):
     default_clk_period = 1e9/8e6
 
     def __init__(self, toolchain="trellis", **kwargs):
-        LatticePlatform.__init__(self, "LFE5U-45F-CABGA381", io=_io, connectors=_connectors,
+        LatticePlatform.__init__(self, "LFE5U-45F-8CABGA381", io=_io, connectors=_connectors,
             toolchain=toolchain, **kwargs)
 
     def create_programmer(self):
diff --git a/litex_boards/partner/targets/hadbadge.py b/litex_boards/partner/targets/hadbadge.py
index ba527b6..1854dbe 100755
--- a/litex_boards/partner/targets/hadbadge.py
+++ b/litex_boards/partner/targets/hadbadge.py
@@ -54,7 +54,6 @@ class _CRG(Module):
 class BaseSoC(SoCSDRAM):
     def __init__(self, toolchain="trellis", sys_clk_freq=int(48e6), sdram_module_cls="AS4C32M8", **kwargs):
         platform = hadbadge.Platform(toolchain=toolchain)
-        platform.toolchain.build_template[1] += " --speed 8" # Add "speed grade 8" to nextpnr-ecp5 # FIXME
 
         # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,