diff --git a/litex_boards/targets/1bitsquared_icebreaker.py b/litex_boards/targets/1bitsquared_icebreaker.py
index 2b61b41..0ab0434 100755
--- a/litex_boards/targets/1bitsquared_icebreaker.py
+++ b/litex_boards/targets/1bitsquared_icebreaker.py
@@ -92,10 +92,15 @@ class BaseSoC(SoCCore):
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
         self.submodules.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
+        self.bus.add_region("sram", SoCRegion(
+                origin = self.bus.regions["psram"].origin + 0*kB,
+                size   = 64*kB,
+                linker = True)
+        )
         if not self.integrated_main_ram_size:
             self.bus.add_region("main_ram", SoCRegion(
-                origin = self.bus.regions["sram"].origin + 64*kB,
+                origin = self.bus.regions["psram"].origin + 64*kB,
                 size   = 64*kB,
                 linker = True)
             )
diff --git a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
index fd2a6ce..65c8956 100755
--- a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
+++ b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
@@ -87,10 +87,15 @@ class BaseSoC(SoCCore):
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
         self.submodules.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
+        self.bus.add_region("sram", SoCRegion(
+                origin = self.bus.regions["psram"].origin + 0*kB,
+                size   = 64*kB,
+                linker = True)
+        )
         if not self.integrated_main_ram_size:
             self.bus.add_region("main_ram", SoCRegion(
-                origin = self.bus.regions["sram"].origin + 64*kB,
+                origin = self.bus.regions["psram"].origin + 64*kB,
                 size   = 64*kB,
                 linker = True)
             )
diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py
index e6c47ad..af79c5b 100755
--- a/litex_boards/targets/kosagi_fomu.py
+++ b/litex_boards/targets/kosagi_fomu.py
@@ -97,10 +97,15 @@ class BaseSoC(SoCCore):
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
         self.submodules.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
+        self.bus.add_region("sram", SoCRegion(
+                origin = self.bus.regions["psram"].origin + 0*kB,
+                size   = 64*kB,
+                linker = True)
+        )
         if not self.integrated_main_ram_size:
             self.bus.add_region("main_ram", SoCRegion(
-                origin = self.bus.regions["sram"].origin + 64*kB,
+                origin = self.bus.regions["psram"].origin + 64*kB,
                 size   = 64*kB,
                 linker = True)
             )